Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters

Abstract

In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 22ENOB, whereas the speed-bound increases by 2ENOB−2 and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2ENOB−1. The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, fs/2.

Single-shot optical neural network

“…This energy value includes peripheral logic and memory access, as well as ∼25 fJ for the MAC operation alone [from (57), scaled to a 7-nm node (58)]. The energy of our single-shot ONN, on the other hand, can be on the order of ∼10 fJ/MAC, including a source wall-plug efficiency of 10% (37,59), a DOE efficiency of 80% (52,60,61), a PD responsivity of 0.2 A/W (40), a TIA sensitivity of 1 μA at 1 GHz (62), an LCoS SLM power consumption of <10 W, and TIA (62), ADC (63,64), DAC (64,65), and nonlinearity (7,11,54) energies of 1 pJ per operation. This overall energy per MAC, including electrical-to-optical and optical-to-electrical conversion, is therefore similar to the cost of one digital electronic MAC, before even considering the expensive electronic data movement in digital accelerators.…”

Integrated photonics modular arithmetic processor

“…As integrated intensity modulators, such as microring resonators, exhibit poor linearity, achieving accurate mapping of operands with a given precision into transmissivities typically requires the utilization of higher precision DACs [36]. In contrast, the favorable linearity of phase modulation and the characteristics of phase summation enable the decomposition of high-bit-width digital-to-analog conversion tasks into parallel lowbit-width tasks, which can significantly reduce system costs and delays [26] and endow the PPMAP for more efficient processing capabilities.…”

“…Additionally, to ensure compatibility with existing digital devices, an optical neuromorphic system operating at ultra-high bandwidth requires high-precision analog-to-digital converters (ADCs) and digital-toanalog converters (DACs) that can match its speed. This requirement poses significant energy consumption challenges [25,26] while also imposing formidable limitations on the performance of the integrated photonics computing system. These "precision challenge" and "converter challenge" have hindered the practical implementation of the intensity-based methods and have necessitated the pursuit of alternative calculation quantity and arithmetic methods for integrated photonics computing.…”

Single-Shot Optical Neural Network

“…Because operations are pipelined to compute 10 6 MACs every ∼1 ns, the system computes ∼10 15 MAC/s -a throughput on the order of petaMAC/s. The energy is ∼10 fJ/MAC, including a source wall-plug efficiency of 10% [37][38][39], PD responsivity of 0.2 A/W [44,45], TIA sensitivity of 1 µA at 1 GHz [47] and TIA, ADC, DAC and nonlinearity energies of 1 pJ per operation [7,12,[47][48][49][50]. We compare these figures to the state of the art in the Discussion section below.…”