Analysis of Efficient 32 Bit Adder Using Tree Grafting Technique

Abstract

Adder with high efficiency and accuracy is the major requirement for electronic circuit design. Here the optical logic gate based adder circuit is designed for better performance analysis of optical input signals varied with the wavelength. Efficiency of the adder can be improved by increasing the speed of operation, reducing the complexity and power consumption. To maintain the high efficiency with accuracy, a new combination of adder has been proposed and tested in this work. A new adder by combining the logics of Brent Kung, Sklansky and Kogge Stone adders by Tree Grafting Technique (BSKTGT) has been tested along with individual Brent Kung, Sklansky, Kogge Stone, Knowles, Han Carlson and Ladner Fischer adders. All the existing and proposed adders have been designed and tested for efficiency with the help of Cadence platform with 45 nm technology. Efficiency in terms of Size reduction, Power reduction, Power Delay Product (PDP) and accuracy in adding 8 bit, 16 bit and 32 bit values had been tested for all the adders and found that the 32 bit BSKTGT adder performed well in all aspects and have produced better efficiency with the power consumption of 52.512426 μW with 3.16% of power saving over Brent Kung adder, utilised an area of 631.191 with 8.55% reduction over Kogge Stone Adder, has the cell count of 132 which is 10.61% reduction over Brent Kung Adder and PDP value of 122.6695 J, which is 0.46% less than that of the Han Carlson Adder.