Analysis of Drain Linear Current Turn-Around Effect in Off-State Stress Mode in pMOSFET

Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range

“…Furthermore, Starkov et al [33] performed an analysis of the turn-around effect in planar 5 V nMOSFETs based on results obtained with the charge-pumping technique; in a more recent paper [34], they carried out modeling of this phenomenon. Such an intricate behavior (when primary and secondary carriers generate/populate traps located in different device sections) was shown by various groups to be typical also for OFF-state stress [35][36][37]. Finally, in our recent work, we demonstrated that II can be the reason for the stimulated recovery of bias temperature instability (BTI) induced by HCD [38].…”

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

“…Therefore, studying the aging mechanisms and modeling of devices under off-sate conditions is crucial for predicting device lifetime and designing aging-aware circuits. In HKMG planar devices, more publications report that off-state stress leads to an increase in on-state current degradation and a decrease in threshold voltage, also called the hot-electron-induced punch-through (HEIP) effect [ 97 , 98 , 99 ], as shown in Figure 10 . This degradation phenomenon is explained as secondary carriers being captured by traps near the drain region, causing a decrease in effective channel length, resulting in reduced threshold voltage and an increase in leakage current.…”

“…Due to the extremely weak gate current, gate metal electromigration is typically overlooked in device and circuit design. However, past research has revealed that a mixed mode of self-heating effects and soft breakdown can lead to gate metal electromigration [ 97 ]. As shown in Figure 14 , TEM images illustrate non-uniform contrast in the M0 layer after a soft breakdown in the on-state, indicating gate metal electromigration.…”