Analysis of drain current saturation behaviour in GaN polarisation super junction HFETs

Abstract

The magnitude of saturation current in a power device significantly impacts its short circuit capability. In conjunction with the unprecedented miniaturisation that GaN offers, there is a compelling rationale to examine this critical parameter in GaN transistors for thermally stable and reliable power converter applications. This article presents a comprehensive analysis of the physical behaviour that yields intrinsically low drain current saturation in GaN Polarisation Super Junction (PSJ) HFETs. The analysis in this work has been performed using electrical characterisation data of conventional and PSJ HFETs, supported by physics-based two-dimensional device simulations. Insight is gained on the differing device architecture-dependent mechanisms that determine the magnitude of drain current density in both types of devices when biased in the saturation region.

Effect of SiO2 Surface Passivation on the Performance of GaN Polarization Superjunction Heterojunction Field Effect Transistors

“…The models employed in this simulation were based on the previously reported PSJ simulation model in ref. [27]. The similar surface charges in defects are based on the research work of refs.…”

An ultra‐fast protection scheme for normally‐on wide bandgap devices

“…The proposed protection circuit is implemented in a single‐phase (1‐Φ) half‐bridge as depicted in Figure 2, which is part of the low side switches of a three‐phase (3‐Φ) buck‐boost inverter for industrial motor drives as shown in Figure 3 [21]. The GaN‐based bidirectional module is constructed by two discrete GaN HEMT in source‐to‐source connection as and or and in Figure 3.…”

“…Furthermore, GaN devices can exhibit the bidirectional current flow capability. In this work, both the desaturation and negative power supply protection circuits are applied to a 1.2 kV polarisation super‐junction (PSJ) GaN FET [20, 21]. Since 1.2 kV PSJ GaN FETs have a limited current rating of 8A, a 650 V/85 A SiC JFET (UJ3N065025K3S) is used to validate the desaturation protection scheme for the higher current operation.…”

Evaluation of turn-off dV/dt controllability and switching characteristics of 1.2 kV GaN polarisation superjunction heterostructure field-effect transistors

“…Moreover, the lateral structure of GaN HEMTs is susceptible to field crowding near gate terminals that prevents them supporting high breakdown voltages. 22,23) To manage the electric field, several field plates are generally used to alleviate the field stress and achieve high-voltage devices. [22][23][24][25][26] However, the use of field plates adds additional processing steps and increases manufacturing costs and area.…”

“…22,23) To manage the electric field, several field plates are generally used to alleviate the field stress and achieve high-voltage devices. [22][23][24][25][26] However, the use of field plates adds additional processing steps and increases manufacturing costs and area. 3) The use of a low-cost Si substrate for higher-voltage devices requires thicker buffer and transition layers due to lattice mismatch 27) and vertical breakdown.…”