Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

Khatak, Anil; Kumar, Manoj; Dhull, Sanjeev Kumar

doi:10.11591/ijece.v8i6.pp4922-4931

Cited by 4 publications

(4 citation statements)

References 20 publications

(26 reference statements)

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“…Cascode Voltage Switch Logic. Renewable comparator at 90 nm CMOS with a supply voltage of 0.7 V is initially simulated (Khatak, Kumar, and Dhull 2018). For high speed applications with low power supply voltage, a new structure of the dynamic latch comparator is proposed.…”

Section: Discussionmentioning

confidence: 99%

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Reddy¹,

Dass²

2021

alinteri

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Aim: The aim of this work is to construct an innovative pMos logic based comparator and analyze the power consumption and compare with the nMos logic based comparator. Material and methods: The comparator is designed by using the Tanner tool version 16.01 for simulation and verification. By varying the length of a transistors in a circuit the power values were obtained. This experiment is performed for 20 different values of length. Results: The power consumption of a pMos logic based comparator was minimum (2.2656 ± 0.37933), followed by the nMos logic based comparator (7.7494 ± 0.41603), the less power consumption seen in pMos logic based comparator significance (.955). Conclusion: The consumption of power by the constructed pMos logic based comparator appears to have less power consumption than the nMos logic based comparator.

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Section: Discussionmentioning

confidence: 99%

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Reddy¹,

Dass²

2021

alinteri

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“…Today, we are considering complex chips comprising high level of power dissipation plus generated heat, and therefore need to be in line with the reduction in the dimensions of microelectronics and digital devices. Currently, commercial microprocessor circuits are available with CMOS transistors with a lateral size in Nano-meter process technology, such miniaturization has led to enormous power and temperature challenges with the presence of billions of transistors on the chip [1,2]. Higher power dissipation leads to increase chip temperature levels that compromising the life of microprocessors due to the addition of new features and performance.…”

Section: Introductionmentioning

confidence: 99%

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Sulaiman¹

2020

IJECE

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The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase. High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (Vth-VDD) which showing satisfactory findings.

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“…Thus, the op-amp comparators designed under such CMOS technologies with restrained supply voltage will not be able to comply with the designer requisites and, thus, adversely affect the performance parameters of abstract circuits that employ these comparators as their core element [10]. Data converters, such as ADC and DAC conversion speed and accuracy, sturdily depend upon the comparator's capability to detect the smallest voltage levels [11,12]. The op-amp comparators with a high slew rate and high gain with high accuracy are to be designed in order to attain these excellent parameters in data converters [13,14].…”

Section: Introductionmentioning

confidence: 99%

“…The rectified signal is a subtracted value taken by subtracting the reference voltage and the common-mode signal [22,24]. and accuracy, sturdily depend upon the comparator's capability to detect the smallest voltage levels [11,12]. The op-amp comparators with a high slew rate and high gain with high accuracy are to be designed in order to attain these excellent parameters in data converters [13,14].…”

Section: Introductionmentioning

confidence: 99%

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Khatak

Kumar

Dhull

2018

JLPEA

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A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

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Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

Cited by 4 publications

References 20 publications

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

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