Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator

Mansingka, Abhinav S.; Radwan, Ahmed G.; Zidan, Mohammed A.; Salama, Khaled N.

doi:10.1109/mwscas.2011.6026596

Cited by 24 publications

(19 citation statements)

References 16 publications

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“…Using a 32-bit implementation, the MLE is found to be 0.1362. While it has been shown that the MLE of such systems decreases with increasing system precision due to lower truncation nonlinearities [26], it remains positive and is thus sufficient to indicate chaos. …”

Section: Chaotic Responsementioning

confidence: 99%

“…The Euler approximation is adopted in this work, as it produces the best chaotic response, occupies the lowest area, and provides the highest throughput [24]. The step size is fixed to be h=2 -3 , the highest possible value to provide the greatest nonlinearity [25], resulting in a nonlinear feedback pipeline [26]:…”

Section: Fully Digital Chaos Generator 1 Digital Realizationmentioning

confidence: 99%

See 1 more Smart Citation

Generalized Hardware Post-processing Technique for Chaos-Based Pseudorandom Number Generators

Barakat¹

2013

ETRI J

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This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations.

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Section: Chaotic Responsementioning

confidence: 99%

Section: Fully Digital Chaos Generator 1 Digital Realizationmentioning

confidence: 99%

Generalized Hardware Post-processing Technique for Chaos-Based Pseudorandom Number Generators

Barakat¹

2013

ETRI J

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“…In particular, multi-scroll chaos generators have been exhaustively studied [9]- [12], wherein the limitations on the dynamic range of analog components and low supply voltages has restricted the number of scrolls that can be realized due to complex circuitry needed for control [13] unless mixed-signal approaches are used [14]. Register transfer level design has been shown to enable reliable and fully digital chaotic oscillators [15]- [17] for direct application in digital systems. Analog limitations are eliminated and repeatability is enabled through ease of register initialization.…”

Section: Introductionmentioning

confidence: 99%

“…However, previous fully digital implementations of the chaotic logistic map had very high hardware requirements [2], [6] and diminished throughput. Jerk-equation based chaotic systems [18] have been digitally implemented and assessed for the effect of bus width and delay elements on the chaotic response [15] and optimized for random number generation [5].…”

Section: Introductionmentioning

confidence: 99%

Fully digital 1-D, 2-D and 3-D multiscroll chaos as hardware pseudo random number generators

Mansingka

Radwan

Salama

2012

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Abstract-This paper introduces the first fully digital implementation of 1-D, 2-D and 3-D multiscroll chaos using the sawtooth nonlinearity in a 3rd order ODE with the Euler approximation. Systems indicate chaotic behaviour through phase space boundedness and positive Lyapunov exponent. Low-significance bits form a PRNG and pass all tests in the NIST SP. 800-22 suite without post-processing. Real-time control of the number of scrolls allows distinct output streams with 2-D and 3-D multiscroll chaos enabling greater controllability. The proposed PRNGs are experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.25%, throughput up to 5.25 Gbits/s and up to 512 distinct output streams with low cross-correlation.

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“…Recently an all digital implementation of differential equation based systems has been introduced [3], [10]. Also a differential equation based multi-scroll system is presented in [11].…”

Section: Introductionmentioning

confidence: 99%

The effect of numerical techniques on differential equation based chaotic generators

Zidan

Radwan

Salama

2011

ICM 2011 Proceeding

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Abstract-In this paper, we study the effect of the numerical solution accuracy on the digital implementation of differential chaos generators. Four systems are built on a Xilinx Virtex 4 FPGA using Euler, mid-point, and Runge-Kutta fourth order techniques. The twelve implementations are compared based on the FPGA used area, maximum throughput, maximum Lyapunov exponent, and autocorrelation confidence region. Based on circuit performance and the chaotic response of the different implementations, it was found that less complicated numerical solution has better chaotic response and higher throughput.

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Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator

Cited by 24 publications

References 16 publications

Generalized Hardware Post-processing Technique for Chaos-Based Pseudorandom Number Generators

Generalized Hardware Post-processing Technique for Chaos-Based Pseudorandom Number Generators

Fully digital 1-D, 2-D and 3-D multiscroll chaos as hardware pseudo random number generators

The effect of numerical techniques on differential equation based chaotic generators

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