Analysis of a New PWM Method for Conducted EMI Reduction in a Field Oriented Controlled Induction Motor

Abstract

The prevalence of EMI noise problems has been considered many times over the past few years, in inverter fed motor control systems. The advent of high speed power devices, and the high dv/dt of switching devices, has resulted in EMI problems and leakage current. This paper describes the application of the newly developed EMI reduction technique of SVPWM in induction motor drives. This newly developed common mode voltage reduction SVPWM technique does not use any zero-voltage vector states for inverter control, hence can restrict the common mode voltage more efficiently than the conventional PWM technique. The validity of the proposed technique is verified through simulation and experimental results. In this paper, by applying the vector control system, the proposed technique is presented as superior in reducing EMI and equal control performance, compared to the conventional space-vector PWM technique.

Predictive modulation schemes to reduce common‐mode voltage in three‐phase inverters‐fed AC drive systems

“…Another cheap and appropriate method for CMV reduction is to improve control algorithm. In this method, in order to reduce or eliminate CMV, different PWM modulation techniques are used which are based on selection of non-zero vectors in two-level three-phase PWM inverters [14,15], and in multilevel PWM inverters the basic idea is to choose vectors that produce zero or the lowest levels of CMV [2,[16][17][18][19]. These PWM modulation techniques that have ever been proposed were based on voltage control, and since some of voltage vectors are eliminated in order to achieve desired CMV, these methods decrease the quality of output waveforms of PWM inverters [unacceptable output currents total harmonic distortion (THD)].…”

A New Active Zero State PWM Algorithm for Reducing the Number of Switchings

“…6 shows simulation waveforms of the line-to-line voltage and the output current of phase-a in both the CSVPWM algorithm and the proposed AZSPWM algorithm, respectively. It can be seen that the output current ripple of the proposed AZSPWM algorithm is slightly higher than that of the CSVPWM algorithm as expected [11], [13], [14].…”

“…9 shows FFT waveforms of the output current of phase-a for the CSVPWM algorithm and the proposed AZSPWM algorithm, and the FFT result is summarized in Table V proposed AZSPWM algorithm. This phenomenon is an expected result, which also occurs in AZSPWM1-3 algorithms [11], [13], [14]. The two algorithms produce on average the same reference voltage vector during a switching period.…”

“…The two algorithms produce on average the same reference voltage vector during a switching period. However, in the proposed AZSPWM algorithm, because two active opposite voltage vectors that are far from the reference voltage vector are utilized instead of real zero voltage vectors (V 0 and V 7 ), the instantaneous error voltage vector of the proposed AZSPWM algorithm is greater than that of the CSVPWM algorithm [11]. Since the frequency of the error voltage vector is the same as the switching frequency, the amplitude of the current at the switching frequency is increased.…”

“…By these algorithms, the CMV is reduced from ± V dc /2 of the conventional space vector PWM (CSVPWM) algorithm to ± V dc /6. However, it can be seen that the output phase current ripple and the DC bus current ripple of the inverter are slightly higher than those of the CSVPWM algorithm via theory, analyses, simulations, and experimental results [11], [13], [14].…”