Analysis of a hybrid OFDM synchronization algorithm for power line communication

Marques, Charles Henrique Dias; Campos, Fernanda; Oliveira, Thiago Rodrigues; Menezes, Alam; Ribeiro, Moisés V.

doi:10.1109/isplc.2010.5479950

Cited by 3 publications

(1 citation statement)

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“…This metric is useful for wireless communications as it increases the robustness to Doppler shifts, but it suffers from the specific conditions of PLC channel. Furthermore, previous PLC synchronization works consider the maximum peak of the auto-correlation metric as the beginning of a symbol [ 23 , 24 ]. This cannot be assumed in practice due to multipath and therefore the first arriving path can be of lower magnitude than a multipath component [ 25 ].…”

Section: Introductionmentioning

confidence: 99%

Efficient Implementation of a Symbol Timing Estimator for Broadband PLC

Nombela

García

Mateos

et al. 2015

Sensors

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Broadband Power Line Communications (PLC) have taken advantage of the research advances in multi-carrier modulations to mitigate frequency selective fading, and their adoption opens up a myriad of applications in the field of sensory and automation systems, multimedia connectivity or smart spaces. Nonetheless, the use of these multi-carrier modulations, such as Wavelet-OFDM, requires a highly accurate symbol timing estimation for reliably recovering of transmitted data. Furthermore, the PLC channel presents some particularities that prevent the direct use of previous synchronization algorithms proposed in wireless communication systems. Therefore more research effort should be involved in the design and implementation of novel and robust synchronization algorithms for PLC, thus enabling real-time synchronization. This paper proposes a symbol timing estimator for broadband PLC based on cross-correlation with multilevel complementary sequences or Zadoff-Chu sequences and its efficient implementation in a FPGA; the obtained results show a 90% of success rate in symbol timing estimation for a certain PLC channel model and a reduced resource consumption for its implementation in a Xilinx Kyntex FPGA.

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Section: Introductionmentioning

confidence: 99%