Analysis of 10 nm Strained Channel Double Gate Ultra-Thin Body Junctionless MOSFET

Abstract

Numerous technological improvements and innovative device architecture have been thoroughly explored and tested for continually downscaling components without compromising on performance metrics. The most simplified structure that has been introduced so far is the junctionless transistors. Junctionless transistors have been shown to exhibit excellent electrical behavior with improved short-channel effects. The major challenges with junctionless based transistors are low ON-current drive and high device variability. Strain engineering has been proven to be a viable option to enhance the ON-current performance of the MOSFET. This work incorporated strained silicon in double gate junctionless ultra-thin body MOSFET (DG-JL UTB MOSFET), which enhanced the mobility of the charge carrier as a result of which ON current behavior improves. The simulated results show 30.2% enhancement in the ON-current, subthreshold current reduced to nearly half, ION/IOFF ratio is increased by three times, and Drain-induced barrier lowering (DIBL) reduced by 25.1% with respect to unstrained device. Analog performance metrics are also calculated for the considered device design. With strained silicon, the value of Gm is increased by more than 30% and transconductance generation factor (TGF) is increased by 28.27% in reference with the unstrained device.