Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Guo, Licheng; Lau, Jason; Chi, Yuze; Wang, Jie; Yu, Cody Hao; Chen, Zhe; Zhang, Zhiru; Cong, Jason

doi:10.1145/3373087.3375332

Cited by 12 publications

(7 citation statements)

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“…AutoBridge does not support pipelining the control signals and the remote accesses to HBM; hence currently it cannot be applied to our sparse accelerator design. Guo et al [35] propose to pipeline the high-fanout signals generated by HLS, although this work does not target multi-die HBM-equipped FPGAs. Zheng et al [36] propose an iterative HLS flow that incorporates place-and-route (PAR) to gradually optimize the critical paths.…”

Section: Related Workmentioning

confidence: 99%

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

Zhou

et al. 2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Sparse linear algebra operators are memory bound due to low compute to memory access ratio and irregular data access patterns. The exceptional bandwidth improvement provided by the emerging high-bandwidth memory (HBM) technologies, coupled with the ability of FPGAs to customize the memory hierarchy and compute engines, brings the potential to significantly boost the performance of sparse linear algebra operators.In this paper we identify four challenges when developing highperformance sparse linear algebra accelerators on HBM-equipped FPGAs -low HBM bandwidth utilization with conventional sparse storage, limited on-chip memory capacity being the bottleneck when scaling to multiple HBM channels, low compute occupancy due to bank conflicts and inter-iteration carried dependencies, and timing closure on multi-die heterogeneous fabrics. We conduct an in-depth case study on sparse matrix-vector multiplication (SpMV) to explore techniques that tackle the four challenges. These techniques include (1) a customized sparse matrix format tailored for HBMs, (2) a scalable on-chip buffer design that combines replication and banking, (3) best practices of using HLS to implement hardware modules that dynamically resolve bank conflicts and carried dependencies for achieving high compute occupancy, and (4) a splitkernel design methodology for frequency optimization. Using the techniques, we demonstrate HiSparse, a high-performance SpMV accelerator on a multi-die HBM-equipped FPGA device. We evaluated HiSparse on a variety of matrix datasets. The results show that HiSparse achieves a high frequency and delivers promising speedup with increased bandwidth efficiency when compared to prior arts on CPUs, GPUs, and FPGAs. HiSparse is available at https://github.com/cornell-zhang/HiSparse. CCS CONCEPTS• Hardware → Hardware accelerators; • Computer systems organization → Data flow architectures.

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Section: Related Workmentioning

confidence: 99%

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

Zhou

et al. 2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…Unlike HDL, the Vivado HLS compiler automatically generates the appropriate pipeline stages, greatly simplifying the task of porting this firmware between devices and speed grades. Several groups have compared Vivado HLS and custom HDL implementations in terms of FPGA resource utilization and maximum fabric speed with mixed results [34]- [38]. While there are no published FPGA resource utilization details for OPFB channelizers with comparable input bandwidth or number of channels, the authors will attempt to cross compare with smaller channelizers and show the resource utilization is better than or consistent with custom HDL approaches.…”

Section: B Oversampled Polyphase Filter Bankmentioning

confidence: 99%

A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

Bailey

Tuthill

Stefanazzi

et al. 2021

IEEE Open J. Circuits Syst.

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Many digital signal processing applications require a channelizer capable of moving sections of the incoming spectrum to baseband quickly and efficiently with minimal spectral leakage and signal distortion. We report the design and implementation of a 4 GHz, 4096-branch, 8-tap, 2/1 oversampled polyphase channelizer implemented on a Xilinx RFSoC. The open-source design consists of only IP cores created using Vivado HLS (C++) and IP cores available in Vivado HLx and System Generator versions 2019.1+. The channelizer was tested using a PYNQ overlay and Jupyter Notebook (Python) hosted on the RFSoC embedded CPU. The design uses 24% of the LUTs, 9% of the DSP48s, and 11% of the BRAMs on the ZCU111 RFSoC evaluation board and meets timing constraints at 512 MHz. The oversampled polyphase channelizer suppresses spectral image components below −60 dB. This design provides the first example of an oversampled polyphase channelizer running on a system on a chip architecture created without direct use of hardware description language. The presented approach leverages high-level design tools and includes source code which can be readily adapted by other researchers and development teams without the need for specialist knowledge in high-performance FPGA design. INDEX TERMS Adaptive computing systems with FPGA components, array signal processing, filter bank theory and design, high-level synthesis, high-performance computing and communication systems, ultra-wideband (UWB) communications.

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“…The system can be used to direct the synthesis to improve the circuit latency. Guo et al [18] observed that the delays induced by signal broadcasting, either by the control logic or the data path, reduce the operating frequency, but they are not included in the delay models of widely used HLS tools, e.g., Vivado HLS. The authors propose techniques to optimize the timing of the implicit broadcasts, such as broadcast-aware scheduling, redundant synchronization pruning, and skid-buffer-based pipeline control.…”

Section: Related Workmentioning

confidence: 99%

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

et al. 2021

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Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use high-level synthesis (HLS) to speed up registertransfer level (RTL) code generation from C++ or OpenCL source code, placement and routing issues, such as congestion, can still prevent achieving an FPGA programming bitstream or dramatically reduce the FPGA implementation performance. Congestion reports from physical design tools refer to thousands of RTL signal names instead of developer-accessible identifiers and statements, considerably complicating the developer understanding and resolution of the issues at the source level. We propose a high-level back-annotation flow that summarizes the routing congestion issues at the source level by analyzing the reports from the FPGA physical design tools and the internal debugging files of the HLS tools. Our flow describes congestion using comments back-annotated on the source code and identifies if the congestion causes are the on-chip memories or the DSP units (multipliers/adders), which are the shared resources very often associated with routing problems on FPGAs. We demonstrate on realistic large designs how the information provided by our flow helps to quickly spot congestion causes at the source level and to solve them using appropriate HLS directives.

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Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Cited by 12 publications

References 0 publications

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

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