11th IET International Conference on AC and DC Power Transmission 2015
DOI: 10.1049/cp.2015.0010
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Analysis and hardware testing of cell capacitor discharge currents during DC faults in half-bridge modular multilevel converters

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Cited by 3 publications
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“…where from the R, L, C series circuit in Figure 8b, fault current in the time domain and the total voltage in the sub-module capacitor are calculated using Equations ( 8) and ( 9), respectively [38,39].…”
Section: Fault Analysis With the Proposed Designmentioning
confidence: 99%
“…where from the R, L, C series circuit in Figure 8b, fault current in the time domain and the total voltage in the sub-module capacitor are calculated using Equations ( 8) and ( 9), respectively [38,39].…”
Section: Fault Analysis With the Proposed Designmentioning
confidence: 99%
“…The equivalent discharging circuit diagram of the capacitors in the SMs in one phase can be seen as a RLC circuit [24]. Where,…”
Section: Fault Characteristic Analysismentioning
confidence: 99%
“…The i k ,f changes at the same frequency with the AC grid, and its maximum value depends on the limiting value of the outer‐loop controller. The I dcf changes very quickly, and it has a bigger influence on the i k ,uf ik,uf=12ik,f+Idcfk=a,b,c The equivalent discharging circuit diagram of the capacitors in the SMs in one phase can be seen as a RLC circuit [24]. Where, Ceq=false(2CSM/Nfalse), Leq=2Lb+Ls+d×l, Req=Rf+d×r.…”
Section: Zone Protection Strategymentioning
confidence: 99%