Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell

Champac, Victor; Mesalles, Javier; Villacorta, Hector; Vargas, F.

doi:10.1007/s10836-021-05955-z

Cited by 3 publications

(3 citation statements)

References 16 publications

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“…where V ′ DD represents power supply, V ′ tp represents threshold voltage at P 2 , p ′ 2 transistor, V ′ tn represents threshold voltage at N 4 , I N4 represents the current through N 4 and I P2 represents the current through P 2 , p ′ 2 , V ′ GS represents drain source voltage of N-type LECTOR based SGFinFETs N 3 , 𝛽 denotes constant used in transistor, this is expressed in Equation (11),…”

Section: Current Equations During Write Operation For Lector Techniqu...mentioning

confidence: 99%

“…At fin‐type field‐effect transistor, the gate electrode design creates the gates with autonomous control on top of channel. FinFET Gate width represents “2nh” here n and h specifies number and height of fins respectively 11–14 . The number of fins maximized to have higher on‐current, which creates maximizes the gate control on the channel, which diminish the Short channel effects 15,16 .…”

Section: Introductionmentioning

confidence: 99%

“…FinFET Gate width represents "2nh" here n and h specifies number and height of fins respectively. [11][12][13][14] The number of fins maximized to have higher on-current, which creates maximizes the gate control on the channel, which diminish the Short channel effects. 15,16 But in SG-FinFET, delay occurs in both read write operation.…”

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confidence: 99%

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Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

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Static random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

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Section: Current Equations During Write Operation For Lector Techniqu...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%