Analysis and design of low noise transconductance amplifier for selective receiver front-end

Duong, Quoc-Tai; Qazi, Fahad; Dąbrowski, Jerzy

doi:10.1007/s10470-015-0629-5

Cited by 1 publication

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“…The circuit is differential and is designed in 65 nm CMOS with elevated supply voltage in the first stage to avoid compression by blockers [68]. The first LNA uses two linearization techniques, namely the derivative superposition and resistive feedback, with NF reduction by double capacitive crosscoupling which results in good noise performance [115] shown in Fig. 3.7.…”

Section: Design Of Two-stage Receiver Front-endmentioning

confidence: 99%

“…This Chapter presents a tunable receiver front-end with high blocker rejection achieved by two-stage impedance transformation. The front-end design is based on a low noise transconductance amplifier (LNTA) [115] which is well suited to reject outof-band blockers due to high ratio between its output impedance and on-resistance of switches used in the impedance transformation circuit.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Integrated Circuits for Wideband Wireless Transceivers

Duong

2016

Linköping Studies in Science and Technology. Dissertations

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The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key challenges encountered in the design of wideband wireless transceiver ICs. It is divided into two parts. Part I describes the design of crucial circuit blocks such as a highly selective wideband radio frequency (RF) front-end and an on-chip test module which are typically found in wireless receivers. The design of high-speed, capacitive DACs for wireless transmitters is included in Part II. The first work in Part I is the design and implementation of a wideband RF frontend in 65-nm CMOS. To achieve blocker rejection comparable to surface-acousticwave (SAW) filters, the highly selective and tunable RF receiver utilizes impedance transformation filtering along with a two-stage architecture. It is well known that the low-noise amplifier (LNA) which forms the first front-end stage largely decides the receiver performance in terms of noise figure (NF) and linearity (IIP3/P1dB). The proposed LNA uses double cross-coupling technique to reduce NF while complementary derivative superposition (DS) and resistive feedback are employed to achieve high linearity. The resistive feedback also enhances input matching. In measurements, the front-end achieves performance comparable to SAW filters with blocker rejection greater than 38 dB, NF 3.2-5.2 dB, out-of-band IIP3 > +17 dBm and blocker P1dB > +5 dBm over a frequency range of 0.5-3 GHz. The second work in Part I is the design of an RF amplitude detector for on-chip test. As the complexity of RF ICs continues to grow, the task of testing and debugging Preface This Ph.D thesis presents my research work during the period January 2011 to January 2016 at the Division of Integrated Circuits and Systems (EKS), Department of Electrical Engineering (ISY), Linköping University, Sweden. I have spent 4 years (80% of the total 5 years) on research and course work of at least 90 Europen Credit Transfer System (ECTS). The 20% left which is 1 year is used for full-time teaching duties. The dissertation is mainly based on the following peer-reviewed journal articles and conference publications:

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Section: Design Of Two-stage Receiver Front-endmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%