Analysis and design of high-speed digital-to-analog converters

Abstract

This Ph.D. thesis pertains to the investigation, design, and monolithic realization of GHz Digital-to-Analog Converters (DACs). State-of-the-art DACs rely heavily on complex digital approaches (calibrations or dynamic-element-matching (DEM)) to achieve high linearity. However, these DACs undesirably suffer from inherent drawbacks such as high switching noise, long (time) latency, and complex GHz synchronization. Consequently, GS/s DACs with innate accuracy (i.e., without calibrations or DEM) are particularly attractive. However, the design of GS/s DACs with innate accuracy is challenging as it usually involves numerous fine-tuning due to sophisticated (often intractable) design trade-offs and the degraded transistor performance at GHz.Further, the testing and verification of GS/s DACs are challenging because of the difficulty associated with the generation of high-speed digital input patterns.