Analysis and design of classical controllers in discrete time to reduce output impedance in UPS's

Astrada, Juan Carlos; Oggier, Germán G.; García, Guillermo

doi:10.23919/rpic.2017.8214329

2017 XVII Workshop on Information Processing and Control (RPIC) 2017

DOI: 10.23919/rpic.2017.8214329

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Analysis and design of classical controllers in discrete time to reduce output impedance in UPS's

Juan Carlos Astrada

Germán G. Oggier

Guillermo García

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Analysis and design of classical controllers in discrete time to reduce output impedance in UPS's

Cited by 1 publication

References 7 publications

Discrete Time Control of Single Phase Inverters for UPS Applications Through a Synchronous Reference Frame

Discrete Time Control of Single Phase Inverters for UPS Applications Through a Synchronous Reference Frame

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