INTELEC - 1979 International Telecommunications Energy Conference 1979
DOI: 10.1109/intlec.1979.4793643
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Analysis and Design of an Adaptive Multi-Loop Controlled Two Winding Buck/Boost Regulator

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Cited by 6 publications
(6 citation statements)
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“…The following performance improvements were observed.and verified in recent modeling and analysis efforts [4,5,6,7]:…”
Section: ) Constant Tf Variable T Variable Tfsupporting
confidence: 71%
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“…The following performance improvements were observed.and verified in recent modeling and analysis efforts [4,5,6,7]:…”
Section: ) Constant Tf Variable T Variable Tfsupporting
confidence: 71%
“…Having identified the three basic functional blocks of a SCM-controlled converter as the power stage, the analog-signal-processor (ASP), and the digital signal processor (SCP), modeling and analysis of these blocks was performed [4,5,6,7]. Subsequently, a common frequency domain block diagram as shown in Fig.…”
Section: System Modeling and Block Diagram Represen Tationmentioning
confidence: 99%
“…A standardized implementation scheme of individual building blocks for various control, command, and protection signals is proposed and actual hardware implementation performed successfully on the three converter configurations: buck, buck/boost, and parallel inverters. The following performance improvements were observed and verified in recent modeling and analysis efforts [4][5][6][7]: 1) high-gain, wide-bandwidth, and precision regulation 2) superior dynamic performances such as audiosusceptibility and transient response 3) stabilization effect by shifting the positive zero on the right-half s-plane to the left-half s-plane 4) control adaptive to the output filter parameter variations due to environmental changes in dutycycle modulations and capacitive loading.…”
supporting
confidence: 67%
“…2 was derived for the three SCM regulators [6]. This common circuit model can be employed to examine the following regulator performance categories: Having identified the three basic functional blocks of an SCM-controlled converter as the power stage, the ASP, and the DSP, modeling and analysis of these block were performed [4][5][6][7]. Subsequently, a common frequency domain block diagram as shown in Fig.…”
mentioning
confidence: 99%
“…Following the modeling approach similar to that described in the author's previous work [6][7][8][9], the small-signal model of the IEEE converter in Fig. 1 is derived as shown in Fig.…”
mentioning
confidence: 99%