Analysis and Design of a Tetrahedral Oscillator

Smith, Richelle L.; Lee, Thomas H.

doi:10.1109/tcsii.2021.3097100

Cited by 6 publications

(2 citation statements)

References 14 publications

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“…Advantages of ring oscillators include compact area, wider tuning range, and low power. [19]- [21]. By using active oscillators connected to a power supply instead of passive resonators, we overcome the problem of dampened oscillations due to nonzero resistance.…”

Section: B Proposed Approach: Polychronous Oscillatory Cnnmentioning

confidence: 99%

Quantum Computing Gate Emulation Using CMOS Oscillatory Cellular Neural Networks

Smith,

Lee

2024

IEEE Trans. Circuits Syst. II

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This paper presents quantum computing gate emulation using polychronous oscillatory cellular neural networks. The oscillatory neural network consists of locally interacting ring oscillators and control switches, in a standard CMOS process. We apply impulse sensitivity function (ISF) theory to model the injection locking of the oscillators. We show the design of universal quantum gate emulation with oscillator circuits. Quantum circuits for the Greenberger-Horne-Zeilinger State and W State are emulated using CMOS oscillators and switches. Spectre simulation results agree with the quantum circuit theory.

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Section: B Proposed Approach: Polychronous Oscillatory Cnnmentioning

confidence: 99%

Quantum Computing Gate Emulation Using CMOS Oscillatory Cellular Neural Networks

Smith,

Lee

2024

IEEE Trans. Circuits Syst. II

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“…A quadrate clock generation circuitry is required as shown in Fig. 19, where four stages of tetrahedral oscillators [27,28] rotating next to each other in sequence are used. Fig.…”

Section: Iq Generation Designmentioning

confidence: 99%

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

He,

Yuan,

Wang

et al. 2024

J. Semicond.

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A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver (TRx) designed in a 28-nm complementary metal-oxide-semiconductor (CMOS) process is presented in this article. A voltage-mode (VM) driver featuring a 4-tap reconfigurable feed-forward equalizer (FFE) is employed in the quarter-rate transmitter (TX). The half-rate receiver (RX) incorporates a continuous-time linear equalizer (CTLE), a 3-stage high-speed slicer with multi-clock-phase sampling, and a clock and data recovery (CDR). The experimental results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board (COB) assembly. The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV (upper-eye), 31 mV (mid-eye), and 28 mV (lower-eye) with an output amplitude of 353 mV single-ended. The recovered 14 GHz clock from the RX exhibits random jitter (RJ) of 469 fs and deterministic jitter (DJ) of 8.76 ps. The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ, at bit-error rate (BER) of 10−5 (0.53 UI). The power dissipation of TX and RX are 125 and 181.4 mW, respectively, from a 0.9-V supply.

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