Analysis and Design of a Context Adaptable SAD/MSE Architecture

Abstract

Design of flexible multimedia accelerators that can cater to multiple algorithms is being aggressively pursued in the media processors community. Such an approach is justified in the era of sub-45 nm technology where an increasingly dominating leakage power component is forcing designers to make the best possible use of on-chip resources. In this paper we present an analysis of two commonly used window-based operations (sum of absolute differences and mean squared error) across a variety of search patterns and block sizes (2 × 3, 5 × 5, etc.). We propose a context adaptable architecture that has (i) configurable 2D systolic array and (ii) 2D Configurable Register Array (CRA). CRA can cater to variable pixel access patterns while reusing fetched pixels across search windows. Benefits of proposed architecture when compared to 15 other published architectures are adaptability, high throughput, and low latency at a cost of increased footprint, when ported on a Xilinx FPGA.

A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos

“…The SAD is commonly used in motion adaptive deinterlacing algorithms and motion estimation algorithms [4]. SAD is defined in (5), and it is the most used distortion criterion because of its efficiency and low cost for a hardware implementation [1].…”

“…These differences are added to create a simple metric of block similarity. A more complex analysis about SAD can be found in [4]…”