Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

Mammei, Enrico; Loi, Fabrizio; Radice, Francesco; Dati, A.; Bruccoleri, Melchiorre; Bassi, Matteo; Mazzanti, Andrea

doi:10.1109/jssc.2014.2345770

Cited by 25 publications

(11 citation statements)

References 21 publications

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“…Our simulations show that in our case, a smaller tap spacing will still result in a successful cancellation of the intersymbol interference (ISI), however, the obtained signal swing will be smaller. For values larger than 10 ps, signal quality starts degrading very quickly which is the same conclusion as in [26].…”

Section: A Convergence Analysissupporting

confidence: 75%

“…As mentioned in section II-B, the delays vary between 9-10 ps. The effect of an LMS loop on an equalizer, where the delays are slightly lower than the symbol spacing, is briefly analyzed in [26]. Our simulations show that in our case, a smaller tap spacing will still result in a successful cancellation of the intersymbol interference (ISI), however, the obtained signal swing will be smaller.…”

Section: A Convergence Analysismentioning

confidence: 92%

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Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

Verplaetse

Keulenaer

Vyncke

et al. 2017

IEEE Trans. Circuits Syst. I

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Abstract-The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for its reduced linearity requirements. In this paper, an adaptive sign-sign least mean square equalizer algorithm is developed applicable for an analog transmit-side feed-forward equalizer (FFE) capable of transforming non-return-to-zero modulation to duobinary (DB) modulation at the output of the channel. In addition to the derivation of the update strategy, extra algorithms are developed to cope with the difficult transmit-receive synchronization. Using an analog six tap bit-spaced equalizer, the algorithm is capable of optimizing DB communication of 100 Gb/s over 1.5-m Twin-Ax cable. Both simulations and experimental results are presented to prove the capabilities of the algorithm demonstrating automated determination of FFE parameters, such that error-free communication is obtained (BER< 10 −13 using PRBS9).Index Terms-Duobinary, feed-forward equalizer, analog equalization, adaptive equalization, least mean squares.

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Section: A Convergence Analysissupporting

confidence: 75%

Section: A Convergence Analysismentioning

confidence: 92%

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

Verplaetse

Keulenaer

Vyncke

et al. 2017

IEEE Trans. Circuits Syst. I

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“…While this is still a low number of FIR taps for a digital filter, this number of taps would already be higher than state-of-the-art reported ≥25 Gbaud analog FIR-equalizer designs (e.g. 7 taps in [11], 6 taps in [12]). An analog FIR-equalizer with 5 half symbol-spaced taps, can compensate around 15 km of fiber with limited penalty.…”

Section: Chromatic Dispersion Compensation Principlementioning

confidence: 85%

“…An analog FIR-equalizer with 5 half symbol-spaced taps, can compensate around 15 km of fiber with limited penalty. To extend the reach to 20 km with 5 analog taps, the tap spacing could be increased slightly towards 0.75 T s (with T s the symbol period), creating a longer filter response without implications on the link performance [11]. The optimal filter parameters in this case for 20 km of fiber are given in Fig.…”

Section: Chromatic Dispersion Compensation Principlementioning

confidence: 99%

Electronic Dispersion Precompensation of Direct-Detected NRZ Using Analog Filtering

Verplaetse

Breyne

Kerrebrouck

et al. 2019

IEEE Photon. Technol. Lett.

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We demonstrate (in real-time) electrical dispersion compensation in direct detection links using analog transmit side filtering techniques. By this means, we extend the fiber reach using a low complexity solution while avoiding digital preprocessing and digital-to-analog converters (DACs) which are commonly used nowadays. Modulation is done using an IQ Mach-Zehnder modulator (MZM) which allows straightforward compensation of the complex impulse response caused by chromatic dispersion in the fiber. A SiGe BiCMOS 5-tap analog complex finite impulse response (FIR) filter chip and/or a delay between both driving signals of the MZMs is proposed for the filter implementation. Several link experiments are conducted in C-band where transmission up to 60 km of standard single-mode fiber (SSMF) of direct detected 28 Gb/s NRZ/OOK is demonstrated. The presented technique can be used in applications where low power consumption is critical.

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“…Equalizer being the major power dissipating block in a coherent optical receiver [17], we studied analog domain implementation of the equalizer as a proof-of-concept validation of the analog processing based transceiver. It may also be seen from the literature that analog domain processing is an attractive choice for low-power equalization in various types of high-speed links [18][19][20][21][22][23][24][25][26][27]. Specifically for optical links, a CMOS receiver with a continuous-time linear equalizer for 30 Gb/s links is reported in [26] and a monolithic optoelectronic IC designed in a 130 nm CMOS process that uses analog domain slope detection based adaptive equalizer is demonstrated in [27] for links with a carrier of 850 nm wavelength.…”

Section: Introductionmentioning

confidence: 99%

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

Nambath

Ashok

Manikandan

et al. 2020

J. Lightwave Technol.

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We present the detailed architecture of an allanalog adaptive equalizer for low-power analog signal processing based coherent optical dual-polarization quadrature phase-shift keying transceivers. The proof of concept equalizer uses the constant modulus algorithm for weight coefficient update. The equalizer, implemented in a 130 nm SiGe BiCMOS technology for 100 Gb/s operation, occupies ∼1.4 mm × 1.35 mm area and draws 1 A current from a 2.5 V supply. Its functionality is validated experimentally for data rates up to 40 Gb/s and by using postlayout circuit simulations for data rates up to 100 Gb/s. The equalizer output after processing with a behavioral Costas loopbased carrier phase recovery and compensation module shows bit error rates well within the hard-decision forward error correction limit for 40 Gb/s single-mode fiber links of length up to 10 km. Performance and power consumption of the equalizer are expected to improve when implemented in advanced CMOS or FinFET technologies. The simple architecture of the analog domain equalizer makes it suitable for analog coherent shortreach interconnects with length less than 10 km and carrier wavelengths of either 1310 nm or 1550 nm.

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Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

Cited by 25 publications

References 21 publications

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

Electronic Dispersion Precompensation of Direct-Detected NRZ Using Analog Filtering

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

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