Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance

Liu, Jiangjiang; Bell, Brian; Truong, Thai V.

doi:10.1109/imsccs.2006.37

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“…Instruction power reduction for VLIW processors has been extensively studied due to the large width of the instructions and the frequency of NOPs for various functional units [4], [8]. Approaches have included instruction compression and scheduling to minimize the instruction bus activity factor [5].…”

Section: Related Workmentioning

confidence: 99%

Hierarchical Instruction Register Organization

Black-Schaffer

Balfour

Dally

et al. 2008

IEEE Comput. Arch. Lett.

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Abstract-This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and examines the benefits from 1) removing the tag overhead, 2) distributing the storage, 3) adding indirection, 4) adding efficient NOP generation, and 5) sharing instruction memory. The result is a hierarchical instruction register organization that provides a 56% energy and 40% area savings over an already efficient Filter Cache.Index Terms-energy-efficient embedded processor architecture, hierarchical and distributed instruction register organization, VLIW instruction delivery

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Section: Related Workmentioning

confidence: 99%