Analog to digital and digital to analog conversion based on stochastic logic

Ortega, Juan Gómez; Janer, Carlos L.; Quero, J.M.; Franquelo, Leopoldo G.; Pinilla, J.; Serrano, Juan Andrés Agapito

doi:10.1109/iecon.1995.483865

Cited by 18 publications

(17 citation statements)

References 4 publications

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“…We note that in some applications, both the Randomizer and De-Randomizer units could be implemented directly through physical interfaces. For instance, in sensor applications, analog voltage discriminating circuits might be used to transform real-valued input and output values into and out of probabilistic bit streams [11]. Furthermore, the total area of the Randomizer and De-Randomizer units could be amortized in some applications (e. g., DSP), which have multiple computations in series.…”

Section: The Randomizer and The De-randomizermentioning

confidence: 99%

A reconfigurable stochastic architecture for highly reliable computing

Qian

Riedel

et al. 2009

Proceedings of the 19th ACM Great Lakes Symposium on VLSI

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Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that operates on probabilistic signals, and so can cope with errors and uncertainty. Techniques for probabilistic analysis are well established. We advocate a strategy for synthesis. In this paper, we present a reconfigurable architecture that implements the computation of arbitrary continuous functions with stochastic logic. We analyze the sources of error: approximation, quantization, and random fluctuations. We demonstrate the effectiveness of our method on a collection of benchmarks for image processing. Synthesis trials show that our stochastic architecture requires less area than conventional hardware implementations. It achieves a large speed up compared to software conventional implementations. Most importantly, it is much more tolerant of soft errors (bit flips) than these deterministic implementations.

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Section: The Randomizer and The De-randomizermentioning

confidence: 99%

A reconfigurable stochastic architecture for highly reliable computing

Qian

Riedel

et al. 2009

Proceedings of the 19th ACM Great Lakes Symposium on VLSI

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“…Low-pass filtering of the stochastic sequence will yield the analog signal level of the results. An approach for converting digital numbers to such pulse sequence was proposed in [5], based on which Ortega [1] constructed DAC and ADC and implemented them as ASIC chips, which is shown in Figure 1. The left side of the doted line is the analog part including an RC low pass filter and an analog comparator while the right side is digital part including a successive approximation register (SAR) and a circuit which transfers digital number to stochastic pulse sequence.…”

Section: The Principle Of Stochastic Adcmentioning

confidence: 99%

“…In this situation digital implementation of ADC will make it possible to integrate the whole system into a single PLD chip or digital Application Specific Integrated Circuits (ASIC). For this reason extensive efforts have been made on developing digitalized DAC and ADC [1 . However, there is not such product in the market so far.…”

Section: Introductionmentioning

confidence: 99%

“…] [ 2] [3] In 1995 Ortega [1] proposed a method to implement 'quasi-digital' ADC and DAC using stochastic logic. The proposed approach was realized as ASIC chips which are almost all digital although it contains a couple of analog components.…”

Section: Introductionmentioning

confidence: 99%

“…This paper is organized as follows. Section 2 gives the principle of stochastic ADC proposed by Ortega [1]. In Section 3 we present the details of the design and implementation of the stochastic ADC using PLDs.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Implementation of a Quasi-digital ADC on PLD

Wang

et al. 2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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This paper presents a new way to implement stochastic logic-based analog-to-digit converters (ADCs) on a programmable logic device (PLD) chip. The proposed implementation is almost all digitalized so that the design can be done by using hardware description language and the results can be easily downloaded into a PLD chip. Both simulation and hardware test results are given. Disciplines Physical Sciences and Mathematics AbstractThis paper presents a new way to implement stochastic logic-based Analog-to-digit converters (ADCs) on a Programmable Logic Device (PLD) chip. The proposed implementation is almost all digitalized so that the design can be done by using hardware description language and the results can be easily downloaded into a PLD chip. Both simulation and hardware test results are given.

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A Stochastic Logic-Based Fuzzy Logic Controller: First Experimental Results of a Novel Architecture

2021

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In stochastic computing (SC) systems numbers are represented with mean values of random binary sequences. This paper introduces a novel fuzzy inference architecture, in which the computational mechanism is based on stochastic logic (SL). First, the basic concept of SL is described, then the architecture of the SL-based fuzzy logic controller (SFLC) is built up systematically using the derived stochastic elements. The second part of the paper demonstrates the application of the proposed techniques, where the SFLC-based control performance is evaluated on a real mechatronic system. The results show that the SL-based approach provides effective and robust control performance, simple architecture and high noise tolerance. The proposed method is also benchmarked against conventional FLCs indicating that the robustness of the stochastic architecture allowed to outperform the benchmark controllers in noisy environments.INDEX TERMS stochastic logic, fuzzy logic controller, fuzzy hardware, self-balancing robot.

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Analog to digital and digital to analog conversion based on stochastic logic

Cited by 18 publications

References 4 publications

A reconfigurable stochastic architecture for highly reliable computing

A reconfigurable stochastic architecture for highly reliable computing

Implementation of a Quasi-digital ADC on PLD

A Stochastic Logic-Based Fuzzy Logic Controller: First Experimental Results of a Novel Architecture

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