Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization

High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

“…We note that the total gate capacitance C gg extracted from the S parameters and given in Table I is lower than the oxide capacitance of 1.6 fF/µm [7], which is in contrast to the simulated and measured total gate capacitances in saturation for deep submicrometer DSD MOSFETs, as reported by Raskin et al [16]. The lower capacitance value for the SB MOSFETs is linked to the presence of the SB as aforementioned, to the quantum effects, and also to the greatly reduced overlap capacitances, as discussed in [11].…”

Fin Field Effect Transistors Performance in Analog and RF for High-k Dielectrics

“…The push for ever increasing device densities is particularly strong in CMOS technologies, such as in the design and fabrication of field effect transistors (FETs) 8 . Scaling FETs to attain higher device density in CMOS results in degradation of performance and/or reliability 9 . The gate of the FinFET is then formed on one or more sides of the fin.…”

“…The gate of the FinFET is then formed on one or more sides of the fin. FinFETs have several advantages, including 9 . FinFET devices need to be isolated from each other, and the source and drain of individual devices need to be isolated to ensure source-to-drain decoupling.…”

“…Severe direct tunneling and reliability problem at extremely small thickness will set a barrier for given material. Alternative dielectric materials with a higher dielectric constant, k, and thus larger physical thickness than SiO 2 will be required to reduce the gate leakage current 9 and provide high on-currents. The implementation of highk dielectrics to the SOI (silicon-on-Insulator) FinFETs improves the scalability and saves chip area.…”

A Subthreshold Swing Model for Symmetric Double-Gate (DG) MOSFETs with Vertical Gaussian Doping

“…Further, both of them assumed that the inversion charge could appear in the entire channel region just opposite to the doped channel and computed the subthreshold swing parameter S (say) for Moldovan et al [12] and Cerderia et al [13,14] suggested that actual devices get generally be doped due to the residual impurities. Further, they had also emphasized that doped channels could provide better control of the threshold voltage (than the undoped devices) without changing the gate material leading to the multi-threshold processes which are of great interests for analog applications [12,15]. Based on the above assumptions, a number of subthreshold swing models [7][8][9][10][11] were also reported for DG MOSFETs with doped channels.…”