Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Abstract

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18- [Formula: see text] technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 μm(2). When operating in the L2 mode, the circuit dissipates 85 [Formula: see text] of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 [Formula: see text] from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

Components of Artificial Neural Networks Realized in CMOS Technology to be Used in Intelligent Sensors in Wireless Sensor Networks

“…Figure 2 shows two popular ways to calculate the distance. From the point of view of the learning process of the neural network, both norms allow obtaining comparable learning results, as shown in our previous works in this area [3,15]. However, the application of the L1 norm is of great importance from the point of view of the computational complexity.…”

“…The ANN worked in the current mode. All main components were designed by us from scratch [13,14,15]. Design of such NNs is a complex task, as after the fabrication no changes are possible.…”

CMOS Perceptron for Vesicle Fusion Classification

“…In another biologically-inspired approach for pattern recognition, the power consumption per channel was achieved at the level of 17 nW [46]. As the third example, we can give a semiconductor implementation of a network with the WTA (Winner Takes All) mechanism, for which the power consumption per channel equals 18.3 µW [47]. As for the implementation of the preprocessor described in the current article, the number of channels is 320, which is the number of multipliers.…”

A Scalable Flexible SOM NoC-Based Hardware Architecture

“…If the high performances, low power consumption or low area occupancy are targeted, an ASIC is preferable to an FPGA implementation. There are some ASIC implementations of SOMs that we found in literature [3,4,5]. An ASIC implementation gives the best performances but is costly, demands high design efforts and has little or no flexibility.…”