Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting

Xu, Biying; Basaran, Bulent; Su, Ming Hsiang; Pan, David Z.

doi:10.1145/3177540.3178245

Cited by 8 publications

(4 citation statements)

References 11 publications

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“…5 shows examples of symmetry constraint and common-centroid constraint. There are other works focusing on regular array-like structure in layouts [54] , monotonic current flow from VDD to VSS [62,63,68] , thermal effects [48] , system signal flow [71] and etc. [16] .…”

Section: Optimization-based Layout Synthesismentioning

confidence: 99%

Challenges and opportunities toward fully automated analog layout design

et al. 2020

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Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated task due to the high design flexibility and sensitive circuit performance. Compared with the advancements of digital IC layout automation, analog IC layout design is still heavily manual, which leads to a more time-consuming and error-prone process. In recent years, significant progress has been made in automated analog layout design with emerging of several open-source frameworks. This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges. We then present recent research trends and opportunities in the field. Finally, we summaries the paper with open questions and future directions for fully-automating the analog IC layout.

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Section: Optimization-based Layout Synthesismentioning

confidence: 99%

Challenges and opportunities toward fully automated analog layout design

et al. 2020

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“…The most widely-used type of constraints are the variations of symmetry constraint [1-4, 6-8, 14-20, 23-26, 28-41], which enforce certain cells to be placed symmetrically. Similar constraints on enforcing the placed locations of matched cells include commoncentroid [19,33,38], regularity [7,26,39], proximity [6,18,25,[33][34][35]41] and etc. Constraints such as monotonic current flow [28,31,36] and thermal effects [19,20] have also been studied to ensure circuit performance.…”

Section: Related Workmentioning

confidence: 99%

“…Such paradigm is often effective but lacks direct ways to optimize the objectives. Other used solving algorithms include mixed-integer-programming (MILP) [39,41] and non-linear programming (NLP) [29,40]. MILP and NLP provide direct approach on optimizing the objectives such as area and wirelength.…”

Section: Related Workmentioning

confidence: 99%

Effective analog/mixed-signal circuit placement considering system signal flow

Zhu

Chen

Liu

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…The conventional analog placement problem usually tries to minimize the objectives including the total area and the total halfperimeter wirelength (HPWL). Besides the non-overlapping constraint between each pair of devices, it also needs to satisfy many other constraints, including matching, proximity group, and symmetry constraints [5][6][7][8][9][10][11]15]. The conventional analog circuit placement problem can be stated as follows:…”

Section: Problem Definitionmentioning

confidence: 99%

Device Layer-Aware Analytical Placement for Analog Circuits

Xu¹,

Li²,

Pui

et al. 2019

Proceedings of the 2019 International Symposium on Physical Design

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The layouts of analog/mixed-signal (AMS) integrated circuits (ICs) are dramatically different from their digital counterparts. AMS circuit layouts usually include a variety of devices, including transistors, capacitors, resistors, and inductors. A complicated AMS IC system with hierarchical structure may also consist of pre-laid out subcircuits. Different types of devices can occupy different manufacturing layers. Therefore, during the layout stage, the devices require co-optimization to achieve high circuit performance. Leveraging the fact that some devices can be built by mutually exclusive layers, they can be carefully designed to overlap each other to effectively reduce the total area and wirelength without degrading the circuit performance. In this paper, we propose an analytical framework to tackle the device layer-aware analog placement problem. Experimental results show that on average the proposed techniques can reduce the total area and half-perimeter wirelength by 9% and 23%, respectively. To verify the routability of the placement results, we also develop an analog global router, which demonstrates that the device layer-aware placement can achieve 18% shorter wirelength during global routing.

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Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting

Cited by 8 publications

References 11 publications

Challenges and opportunities toward fully automated analog layout design

Challenges and opportunities toward fully automated analog layout design

Effective analog/mixed-signal circuit placement considering system signal flow

Device Layer-Aware Analytical Placement for Analog Circuits

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