Analog perceptron circuit with DAC-based multiplier

Ishiguchi, Yoritaka; Isogai, Daishi; Osawa, T.; Nakatake, Shigetoshi

doi:10.1016/j.vlsi.2018.05.010

Cited by 3 publications

(8 citation statements)

References 4 publications

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“…The offset of the final output is negligible and has only hundreds of microvolts, and all the sin waves are adjusted to the appropriate position so that they can be observed clearly. The measured results are consistent with the simulation results reported in the work by [ 24 ].…”

Section: A Measurement-verified Perceptron Chipsupporting

confidence: 92%

“…In the circuit under test, there is a sum module following after the outputs of three multipliers, which is constituted by an OPAMP-based adder and an inverting amplifier. The whole circuit is slightly different from that reported in the work [ 24 ]. This is because in the previous design, it is found that the feedback current noise arising from the outputs of DACs can affect the biasing of each other, leading to the waveform distortion in the final output.…”

Section: A Measurement-verified Perceptron Chipcontrasting

confidence: 60%

“…Aimed at an analog front-end of a sensor node, Ishiguchi et al propose an analog perceptron circuit with DAC-based multiplier in the work [ 24 ] to improve the sensing information. An analog perceptron circuit with a DAC-based multiplier (namely, Cir.01.)…”

Section: A Measurement-verified Perceptron Chipmentioning

confidence: 99%

“…Aiming at the advanced sensor nodes, such as the biological sensor systems introduced in [ 22 , 23 ], Ishiguchi (our group member) et al has proposed an analog perceptron circuit with a DAC-based multiplier in [ 24 ]. In comparison with the traditional sensor system where the central processing unit and signal processing unit are necessary.…”

Section: Introductionmentioning

confidence: 99%

“…Analog VLSI implementations are preferable for a sensor node as they have lower power and a smaller device area. The preliminary results provided in [ 24 ] is the base of developing our research. In this work, an analog perceptron comprising of DAC-based multipliers and phase shifters is fabricated in a 0.6 µm/±2.5 V CMOS process.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

Geng

Sun

Nakatake

2020

Sensors

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Perceptron is an essential element in neural network (NN)-based machine learning, however, the effectiveness of various implementations by circuits is rarely demonstrated from chip testing. This paper presents the measured silicon results for the analog perceptron circuits fabricated in a 0.6 μm/±2.5 V complementary metal oxide semiconductor (CMOS) process, which are comprised of digital-to-analog converter (DAC)-based multipliers and phase shifters. The results from the measurement convinces us that our implementation attains the correct function and good performance. Furthermore, we propose the multi-layer perceptron (MLP) by utilizing analog perceptron where the structure and neurons as well as weights can be flexibly configured. The example given is to design a 2-3-4 MLP circuit with rectified linear unit (ReLU) activation, which consists of 2 input neurons, 3 hidden neurons, and 4 output neurons. Its experimental case shows that the simulated performance achieves a power dissipation of 200 mW, a range of working frequency from 0 to 1 MHz, and an error ratio within 12.7%. Finally, to demonstrate the feasibility and effectiveness of our analog perceptron for configuring a MLP, seven more analog-based MLPs designed with the same approach are used to analyze the simulation results with respect to various specifications, in which two cases are used to compare to their digital counterparts with the same structures.

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Section: A Measurement-verified Perceptron Chipsupporting

confidence: 92%

Section: A Measurement-verified Perceptron Chipcontrasting

confidence: 60%

Section: A Measurement-verified Perceptron Chipmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

Geng

Sun

Nakatake

2020

Sensors

Self Cite

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High-Throughput Low Power Area Efficient 17-bit 2’s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices

Romaine

Martín

2022

IEEE Access

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In this manuscript the authors, design new hardware efficient combinational building blocks for a Multi Layer Perceptron (MLP) unit which eliminates the need for hardware generic Digital Signal Processing (DSP) units and also eliminates the need for on-chip block RAMs (BRAMs). The components were designed to minimise power and area consumption without sacrificing throughput. All designs were validated in a Field Programmable Gate Array (FPGA) and compared against unrestricted CPU-MATLAB implementations. Furthermore, a (2,2,2,2) MLP with back propagation was implemented and tested in a FPGA showing a total hardware utilisation of just 3782 LUTs, and no DSP or BRAMs. The MLP was also built in a Application Specific Integrated Circuit (ASIC) using a 130 nm technology by Skywater 130A. The results show that the area occupation was just 0.12 mm 2 and consumed just 100 mW at 100 MHz input stimulus.

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