Analog Memristive CAMs for Area- and Energy-Efficient Reconfigurable Computing

Lima, João Paulo Cardoso de; Moura, Rafael Fão de; Carro, Luigi

doi:10.1109/tcsii.2020.2983005

Cited by 2 publications

(5 citation statements)

References 25 publications

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“…Content addressable memory (CAM) is an attractive hardware solution for applications that significantly rely on high-speed search, match, and retrieve operations [1][2][3][4] . Unlike conventional SRAM, that takes several cycles for a search operation, a CAM directly performs the search within its pre-stored content in a parallel fashion with potential single cycle access, naturally realizing in-memory computing (IMC).…”

Section: Introductionmentioning

confidence: 99%

“…When both inputs are resistance type, usually the design is used for content retrieval applications where both operands are stored in the memory 3,8,9 . While in case one operand is voltage and being compared to the second operand stored as resistance, it will benefit real-time applications for query where one vector (voltage) need to be matched with semi-static data (RRAM) 1,2,10,11 . In this work, the focus is on the voltage-resistance input operands representation.…”

Section: Introductionmentioning

confidence: 99%

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RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

Halawani

Kilani

Hassan

et al. 2021

Preprint

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Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered.The proposed design uses 65nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2 , consumes 13.6 pJ of energy per 1k query within 10 ns clock cycle for 10 classes. It shows a reduction of ∼ 31× in area and ∼ 3× in energy consumption compared to fully digital ASIC implementation using 65nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

Halawani

Kilani

Hassan

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Content addressable memory (CAM) is an attractive hardware solution for applications that significantly rely on high-speed search, match, and retrieve operations [1][2][3][4] . A CAM directly performs the search within its prestored content in a parallel fashion with potential single cycle access, naturally realizing in-memory computing (IMC) 5,6 .…”

mentioning

confidence: 99%

mentioning

confidence: 99%

“…For example, authors in 12 are proposing the usage of 2T2MR-CMOL (CMOS+Molecular) architecture to increase density and reduce energy consumption along with a novel scheduling method. While in 1 , authors proposed multi-level memory cells in the design of CAM-based reconfigurable architecture. Each cell consists of a 6T2R structure to represent the three bits with two search lines (SL) and one ML.…”

mentioning

confidence: 99%

See 1 more Smart Citation

RRAM-based CAM combined with time-domain circuits for hyperdimensional computing

Halawani

Kilani

Hassan

et al. 2021

Sci Rep

View full text Add to dashboard Cite

Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM (RRAM)-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered. The proposed design uses 65 nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2, consumes 13.6 pJ of energy per 1 k query within 10 ns clock cycle. It shows a reduction of ~ 31 × in area and ~ 3 × in energy consumption compared to fully digital ASIC implementation using 65 nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

show abstract

Analog Memristive CAMs for Area- and Energy-Efficient Reconfigurable Computing

Cited by 2 publications

References 25 publications

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

RRAM-based CAM combined with time-domain circuits for hyperdimensional computing

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