Analog matching properties process dependency on MIM capacitors

Ping, Chu Tsui; Ling, Tee Pei; Lau, G.

doi:10.1109/rsm.2011.6088329

Cited by 3 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Equation (18) indicates that by means of inverse control signal and corresponding symmetric capacitor layout, the firstorder gradient error is cancelled and only common-mode offsets are left in the differential residue transmission. This can be verified by circuit simulation.…”

Section: Gradient-mismatch Cancelling Techniquementioning

confidence: 99%

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

Zhao¹,

Wei²,

Yang³

et al. 2014

J. Semicond.

View full text Add to dashboard Cite

This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-m CMOS technology, this ADC occupies 10.16-mm 2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

show abstract

Section: Gradient-mismatch Cancelling Techniquementioning

confidence: 99%

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

Zhao¹,

Wei²,

Yang³

et al. 2014

J. Semicond.

View full text Add to dashboard Cite

show abstract

Reliability improvement based on silicon nitride MIM capacitors for mixed-signal and RF applications

Wang

Cheng

Chien

2016

2016 China Semiconductor Technology International Conference (CSTIC)

View full text Add to dashboard Cite

Influences Study on MIM capacitors' reliability

Ping

Yang

Ling

2012

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)

Self Cite

View full text Add to dashboard Cite

Reliability assessment tests are used to evaluate the quality of different process schemes of MIM capacitors. Typically, VRAMP tests can be used to check for extrinsics; which are common and popular method used for evaluating yield issues and early life failures (in which the product failures in ppm level); while TDDB tests are used to determine the intrinsic quality of the capacitor dielectrics; thus the lifetime will be extrapolated accordingly from its dependency from accelerated tests at different higher stress conditions down to the corresponding use condition. In this paper, we will summarize the different approaches of making high capacitance density MIM capacitors in two dimensions -thickness or area: that is to say to achieve with thinner dielectrics or by using stack layers (i.e. single, double, or even triple stacked up in parallel). Comparisons are made in terms of breakdown voltages, leakages, linearity, RF Q-factors and mainly the reliability impact: extrinsics level and intrinsic lifetime even with the same capacitance density. Further Study on various process variants with reliability assessment has also been done, and will be discussed here as well.

show abstract

Analog matching properties process dependency on MIM capacitors

Cited by 3 publications

References 6 publications

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

Reliability improvement based on silicon nitride MIM capacitors for mixed-signal and RF applications

Influences Study on MIM capacitors' reliability

Contact Info

Product

Resources

About