Analog integrated circuit design [Book Review]

Johns, D.A.; Martin, Kenneth W.; Wiley, J. D.

doi:10.1109/mcd.2000.876905

Cited by 560 publications

(917 citation statements)

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“…There are many possible architectures which can be used for realizing the required DAC structure with the constraints given above, e.g., resistor-string (R-string), current steering DAC, charge accumulation DAC and segmented DAC [7]. It has been shown in [11], that a resistor-string DAC architecture occupies lesser area, consumes less power, simple in design and can generate the two reference levels as described above.…”

Section: Continuous Time Dacmentioning

confidence: 99%

“…A final DAC architecture is presented, which is used in the design and block diagram is shown in fig-10. The segmented m × n resistor-string DAC consists of two segments, where the first string with m resistors, resolves the Most Significant Bits (MSBs) and the second substring with n resistors, resolves the Least Significant Bits (LSBs) [7].…”

Section: Segmented Resistor-string Dacmentioning

confidence: 99%

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A Continuous-Time Adc and Digital Signal Processing System for Smart Dust and Wireless Sensor Applications

Rao¹,

Kesav²

2013

IJRET

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Section: Continuous Time Dacmentioning

confidence: 99%

Section: Segmented Resistor-string Dacmentioning

confidence: 99%

A Continuous-Time Adc and Digital Signal Processing System for Smart Dust and Wireless Sensor Applications

Rao¹,

Kesav²

2013

IJRET

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“…Proposition 2 gives a nonlinear transformation for an (suboptimal) MMSE compander for any distribution. 1]; and the compander with compressor Y = F X (X) is an optimal/suboptimal MMSE quantizer of X, especially when X is quantized with high rate.…”

Section: Mmse Compandermentioning

confidence: 99%

“…On one hand, many input signals are continuous analog signals, therefore, quantization is indispensable for analog-to-digital converters (ADC) [1], which are important components of many digital products. On the other hand, with the exponential growth of usage of computers and Internet, countless digital contents, especially digital images and videos, demand signal compression for efficient storage and transmission.…”

Section: Introductionmentioning

confidence: 99%

Adaptive quantization using piecewise companding and scaling for Gaussian mixture

Lei

2012

Journal of Visual Communication and Image Representation

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“…Another possible way to increase the slew rate and ensure that all transistors remain in saturation during slewing is to clamp the cascode nodes with diode-connected devices [158].…”

Section: Folded Cascode Otamentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Analog integrated circuit design [Book Review]

Cited by 560 publications

References 0 publications

A Continuous-Time Adc and Digital Signal Processing System for Smart Dust and Wireless Sensor Applications

A Continuous-Time Adc and Digital Signal Processing System for Smart Dust and Wireless Sensor Applications

Adaptive quantization using piecewise companding and scaling for Gaussian mixture

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

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