Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron

Khodabandehloo, Golnar; Mirhassani, Mitra; Ahmadi, M.

doi:10.1109/tvlsi.2011.2109404

Cited by 76 publications

(41 citation statements)

References 20 publications

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“…Current proportional to z n next enters a transistor based analog neuron circuit that executes tanh activation function (f ) of equation (2) [42,43]. Thus output voltage of neuron circuit corresponds to y n at output node n ( Fig.…”

Section: Design Of Crossbar Fullymentioning

confidence: 99%

On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network

Dey

Sharda

Saxena

et al. 2019

2019 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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On-chip learning in a crossbar array based analog hardware Neural Network (NN) has been shown to have major advantages in terms of speed and energy compared to training NN on a traditional computer. However analog hardware NN proposals and implementations thus far have mostly involved Non Volatile Memory (NVM) devices like Resistive Random Access Memory (RRAM), Phase Change Memory (PCM), spintronic devices or floating gate transistors as synapses. Fabricating systems based on RRAM, PCM or spintronic devices need in-house laboratory facilities and cannot be done through merchant foundries, unlike conventional silicon based CMOS chips. Floating gate transistors need large voltage pulses for weight update, making on-chip learning in such systems energy inefficient. This paper proposes and implements through SPICE simulations on-chip learning in analog hardware NN using only conventional silicon based MOSFETs (without any floating gate) as synapses. We first model the synaptic characteristic of our single transistor synapse using SPICE circuit simulator and benchmark it against experimentally obtained current-voltage characteristics of a transistor. Next we design a Fully Connected Neural Network (FCNN) crossbar array using such transistor synapses. We also design analog peripheral circuits for neuron and synaptic weight update calculation, needed for on-chip learning, again using conventional transistors. Simulating the entire system on SPICE circuit simulator, we obtain high training and test accuracy on the standard Fisher's Iris dataset, widely used in machine learning. We also account for device variability and noise in the circuit, and show that our circuit still trains on the given dataset. We also compare the speed and energy performance of our transistor based implementation of analog hardware NN with some previous implementations of NN with NVM devices and show comparable performance with respect to on-chip learning. Easy method of fabrication makes hardware NN using our proposed conventional silicon MOSFET really attractive for future implementations.

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Section: Design Of Crossbar Fullymentioning

confidence: 99%

On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network

Dey

Sharda

Saxena

et al. 2019

2019 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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“…In this paper, the backpropagation algorithm is similar to the backpropagation with gradient descent shown in [4]. However, after the calculation of the updated weight , it is binarized to w either high w high and low values w low , or their negative alternatives −w high and −w low .…”

Section: Hardware Implementation Of Bnnmentioning

confidence: 99%

“…In addition, due to the limitations of the levels of the memristive devices, BNN hardware implementation can be built with the existing binary memristive devices. The memristive devices have been proven to be efficient for various architectures in terms of scalability, power consumption and on-chip area [3,4,5,6,7,8,9,10,11,12].…”

mentioning

confidence: 99%

Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing

Krestinskaya

James

2018

2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)

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The memristive crossbar aims to implement analog weighted neural network, however, the realistic implementation of such crossbar arrays is not possible due to limited switching states of memristive devices. In this work, we propose the design of an analog deep neural network with binary weight update through backpropagation algorithm using binary state memristive devices. We show that such networks can be successfully used for image processing task and has the advantage of lower power consumption and small on-chip area in comparison with digital counterparts. The proposed network was benchmarked for MNIST handwritten digits recognition achieving an accuracy of approximately 90%.

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“…Conven tional lumped neurons require adjustments at the circuit level when the number of inputs to the layer changes. It has been shown that a distributed, resistive-type configuration prevents the neurons from going into saturation and to act like a hard limit function when the number of network inputs increases [1], [5]- [7].…”

Section: Proposed Modul Ar N Eur Al N Etworkmentioning

confidence: 99%

A modular mixed-signal CVNS neural network architecture

Saffar

Mirhassani

Ahmadi

2015

2015 International Joint Conference on Neural Networks (IJCNN)

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In this paper design and implementation of a modular mixed-signal feed-forward neural network is presented. The network is implemented based on the Continuous Valued Number System (CVNS) arithmetic with neurons distributed in the network. Synapse weights are implemented on the chip using capacitive analog memories. Weight values are stored as the CVNS values and are refreshed and updated using the overlap between the CVNS digits. Current-mode logic is used for implementation in order to simplify the circuit design, and especially addition, which resulted in reduced power and area consumption. The distributed nature of the neurons allows for expansion of the network into larger networks. Individual modular layers are fabricated in TSMC CMOS 180nm, and are used to form different network sizes. The module is used to configure two proof of concept examples, a 2 -2 -1 and a 3 -2 -1 network to solve the XOR problem. Results of test and verification presented in this paper show the network flexibility of the proposed design to form various network configurations.

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Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron

Cited by 76 publications

References 20 publications

On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network

On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network

Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing

A modular mixed-signal CVNS neural network architecture

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