Analog Frontend for a Passive 5.8-GHz RFID Transponder in 130-nm CMOS Technology

Funke, Dominic A.; Bredendiek, Christian; Pohl, Nils

doi:10.23919/eumc50147.2022.9784344

Cited by 1 publication

(1 citation statement)

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“…Near-field integrated antenna structure in [30], only achieves mm-range of communication. Reference [31] provides a relatively comparable sensitivity of -11 dBm at 5.8 GHz range, in a 130 nm technology and with a fully passive charge-pump structure, however, the AFE chip is limited to a simplified structure including the harvester unit, limiter, and backscattering modulator. V. CONCLUSION This paper presented the design and implementation of a fully integrated tag chip to be used for the next generation of passive RFID systems at 5.8 GHz.…”

Section: Data Management and Digital Control Unitsmentioning

confidence: 99%

A Sub-Threshold Microwave RFID Tag Chip, Compatible With RFID MIMO Reader Technology

Haddadian,

Scheytt,

vom Bögel

et al. 2023

IEEE J. Radio Freq. Identif.

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We present a fully integrated radio frequency identifications transponder chip operating at 5.8 GHz, which is compatible with the class-1 generation-2 of the Electronic Product Code protocol (EPC-C1 G2). The tag chip including the analog front-end and the digital baseband processor, are designed in the sub-threshold regime (0.5 V) with a total supply current of less than 50 µA. As a power scavenging unit, a singlestage differential-drive rectifier structure is designed and fabricated with standard threshold voltage (SVT) MOS elements in a commercial 65-nm CMOS process, to provide 0.8 V of rectified voltage. Measurements performed on the fabricated single-stage structure show a maximum power conversion efficiency of 69.6% for a 22 kΩ load and a sensitivity of -12.5 dBm, which corresponds to more than 1 m of reading range. The power conversion efficiency at this range is about 64%.

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Section: Data Management and Digital Control Unitsmentioning

confidence: 99%