Analog Circuit Design in Nanoscale CMOS Technologies

Lewyn, L.L.; Ytterdal, Trond; Wulff, Carsten; Martin, Kenneth W.

doi:10.1109/jproc.2009.2024663

Cited by 174 publications

(95 citation statements)

References 40 publications

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“…The conclusions can be made based on how the technology downscaling affects the different process and device parameters. Table 9.1 shows the scaling factor corresponding to the relevant device parameters [97]. The technology downscaling allows a higher oxide capacitance per unit area, a lower gate width and lower overlap and parasitic capacitances.…”

Section: / F and Thermal Noisementioning

confidence: 99%

“…It is important to investigate the evolution of this noise when using more advanced technologies. Indeed, the gate leakage current increases by several orders of magnitude when downscaling from 180 nm to 65 nm technologies [97]. Based on (4.45), the shot noise associated to the gate leakage current is hence expected to increase significantly.…”

Section: Leakage Current Shot Noisementioning

confidence: 99%

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Ultra Low Noise CMOS Image Sensors

Boukhayma

2018

Springer Theses

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Section: / F and Thermal Noisementioning

confidence: 99%

Section: Leakage Current Shot Noisementioning

confidence: 99%

Ultra Low Noise CMOS Image Sensors

Boukhayma

2018

Springer Theses

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“…Moreover, the W/L trimming for the given circuit composed of MOS transistors would in− volve extensive integration into the HSPICE simulation engine which in consequence may limit the usability of the migration software only for the particular technology and associated version of the simulator. This becomes an impor− tant issue as we consider the number of nonlinearities intro− duced by novel nanoscale CMOS fabrication processes [17]. Besides the built−in HSPICE optimization routines are generally worse suited for parameter matching in compari− son to direct search methods [18].…”

Section: Automation Of Cmos Technology Migration Illustrated By Rgb Tomentioning

confidence: 99%

Automation of CMOS technology migration illustrated by RGB to YCrCb analogue converter

Naumowicz

Melosik

Katarzyński

et al. 2013

Opto-Electronics Review

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The paper illustrates a practical example of technology migration applied to the colour space converter realized in CMOS technology. The element has analogue excitation and response signals expressed in current mode. Such converter may be incorporated into an integrated vision sensor for preconditioning acquired image data. The idea of a computer software tool supporting the automated migration and design reuse is presented as the major contribution. The mentioned tools implement the Hooke-Jeeves direct search method for performing the multivariable optimization. Our purpose is to ensure transferring the circuit between usable fabrication technologies and preserving its functional properties. The colour space converter is treated as the case study for performance evaluation of the proposed tool in cooperation with HSPICE simulation software. The original CMOS technology files for Taiwan semiconductor (TSMC) plant were utilized for the research. The automated design migration from 180 nm into 90 nm resulted with obtaining compact IC layout characterized by a smaller area and lower power consumption. The paper is concluded with a brief summary that proves the usability of the proposed tool in designing CMOS cells dedicated for low power image processing.

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“…If we were to use standard oxide transistors the V DS of M 3 , M 4 and M 2 would be too large. At high V DS the transistors can be damaged by hot-carrier injection [13]. Using thick oxide transistors removed this challenge, but for the switch transistor we've used a low-threshold thin oxide device to reduce the switch resistance.…”

Section: Bootstrapped Switchesmentioning

confidence: 99%

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

Wulff

Ytterdal

2010

Analog Integr Circ Sig Process

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We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 2.5-bit to 7.05-bit. The ADC is manufactured in a 90 nm CMOS technology, with a core area of 0.85 mm 9 0.35 mm, a 1.2 V supply for the core and 1.8 V for the input switches. It has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5 mW at 60 MS/s.

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Analog Circuit Design in Nanoscale CMOS Technologies

Cited by 174 publications

References 40 publications

Ultra Low Noise CMOS Image Sensors

Ultra Low Noise CMOS Image Sensors

Automation of CMOS technology migration illustrated by RGB to YCrCb analogue converter

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

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