Analog and Mixed Signal Diagnosis Flow Using Fault Isolation Techniques and Simulation

Abstract

Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

High Aspect Ratio Vertical Bipolar Junction Transistor NPN Device Fault Isolation and Analysis Techniques

“…A common concern with this type of result is also the possibility of an upstream defect driving the NPN abnormally when a point emission or OBIRCH signal is not observed. Careful consideration of the circuit is sometimes useful in deciding next steps [8]. At the very least, these signatures begin to help isolate the analog device(s) of interest.…”