An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing

Rollins, Nathaniel; Arnesen, Adam; Wirthlin, Michael

doi:10.1109/naecon.2008.4806545

Cited by 2 publications

(4 citation statements)

References 6 publications

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“…Prior to the CHREC XML presented in this paper, another XML schema was created for representing IP cores in a reconfigurable computing environment [6]. This initial schema addresses some of the limitations of IP-XACT and better supports FPGA IP used in reconfigurable computing.…”

Section: Chrec Xml: a Layered Xml Schema For Reconfigurable Computingmentioning

confidence: 99%

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A multi-layered XML schema and design tool for reusing and integrating FPGA IP

Arnesen

Rollins

Wirthlin

2009

2009 International Conference on Field Programmable Logic and Applications

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Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and verified intellectual property (IP) cores. This paper presents CHREC XML, a XML schema that facilitates IP reuse by encapsulating the details of reusable IP cores at multiple levels of abstraction. This schema is independent from any design language or tool and can be used by any tool to understand many details about the interface of a reusable circuit. An IP integration tool was also created based on this schema to demonstrate the ease of IP reuse when cores are described in this meta-data description. This IP integration tool allows a designer to easily select and integrate IP cores from a variety of languages/tools and automatically run the appropriate tools to generate the cores in a form usable by downstream implementation tools.

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Section: Chrec Xml: a Layered Xml Schema For Reconfigurable Computingmentioning

confidence: 99%

“…The RTL layer describes the low-level details of an IP core and is very similar to the initial schema described in [6]. It includes the naming of ports and a mapping of these ports to the actual ports listed in HDL.…”

Section: Layer 1: Rtl Layermentioning

confidence: 99%

A multi-layered XML schema and design tool for reusing and integrating FPGA IP

Arnesen

Rollins

Wirthlin

2009

2009 International Conference on Field Programmable Logic and Applications

Self Cite

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“…Pero XML no sólo se ha utilizado para la descripción de hardware, también es un lenguaje adecuado para encapsular cores. En [RAW08] proponen un XML-Schema que permite encapsular IPs descritos en diferentes lenguajes, ya sean los tradicionales VHDL o Verilog, o los generados a partir de lenguajes de alto nivel. El objetivo es presentar un encapsulado que ofrezca los detalles de las diferentes implementaciones como meta-datos, para que las herramientas de diseño puedan de manera automática evaluar, manipular e instanciar estos cores.…”

Section: Xml Para El Encapsulado De Hardwareunclassified

“…El encapsulado propuesto en [RAW08] incluye la posibilidad de describir los parámetros del componente y la especificación de los puertos de la interfaz. En la especificación de los parámetros se permite evaluarlos mediante funciones.…”

Section: Xml Para El Encapsulado De Hardwareunclassified

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

Marcos¹

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This PhD. thesis addresses the design and implementation of signal processing applications using reconfigurable FPGA platforms. This kind of platform exhibits high logic capability, incorporates dedicated signal processing elements and provides a low cost solution, which makes it ideal for the development of signal processing applications, where intensive data processing is required in order to obtain high performance.However, the cost associated to the hardware development on these platforms is high. While the increase in logic capacity of FPGA devices allows the development of complete systems, high-performance constraints require the optimization of operators at very low level. In addition to time constraints imposed by these applications, Area constraints are also applied related to the particular device, which force to evaluate and verify a design among different implementation alternatives. The design and implementation cycle for these applications can be tedious and long, being therefore normal that new FPGA models with a greater capacity and higher speed appear before completing the system implementation. Thus, the original constraints which guided the design of the system become useless.Different methods can be used to improve the productivity when developing these applications, and consequently shorten their design cycle. This PhD. Thesis focuses on the reuse of hardware components previously designed and verified. Although conventional HDLs allow the reuse of components already defined, their specification can be improved in order to simplify the process of incorporating new design components. Thus, a first part of the PhD. Thesis will focus on the specification of designs based on predefined components. This specification improves and simplifies the process of adding components to a description, but it also seeks to improve the quality of the design specified with better configuration options and even offering to report on features of the description.Hardware reuse of a component for its integration into a system largely depends on the information it offers. In this sense the conventional HDLs only provide together with the component description, the input/output interface and a set of parameters for its configuration, while other information is usually provided by external documentation. In the second part of the Thesis we will propose a formal way of encapsulation which aims to incorporate with the component description information that can be useful for its integration into other designs. This information will include features of the own implementation, but it will also support component configuration, and even information on how to configure and connect the component to carry out a function.Finally, the fast Fourier transform (FFT) will be chosen as a well-known signal processing application. It will be used as case study to illustrate the possibilities of porposed v specification and encapsulation formalisms. The objective of the FFT design is not only to show practical examples of the proposed s...

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An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing

Cited by 2 publications

References 6 publications

A multi-layered XML schema and design tool for reusing and integrating FPGA IP

A multi-layered XML schema and design tool for reusing and integrating FPGA IP

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

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