2019
DOI: 10.1002/mop.31794
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An X‐band single‐pull class A/B power amplifier in 0.18 μm CMOS

Abstract: We report a compact single‐pull X‐band power amplifier (PA) operating at the class AB utilizing on‐chip transformers in 0.18‐μm 1P6M CMOS technology. Designed X‐band PA includes the interstage matching network and the output power combiner by utilizing on‐chip transformers to achieve small area occupation with improved power added efficiency (PAE). A series RC network is employed between gate and drain of the MOS to provide stable operation with improved bandwidth. The designed PA measures the saturated output… Show more

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Cited by 4 publications
(3 citation statements)
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“…The shunt RC feedback circuit used in [14] can increase bandwidth, flatten the gain and reduce the distortion. However, the peak gain will be degraded [30]. The neutralization capacitor technique can also achieve stability and increase the bandwidth of PA, and better gain can be maintained.…”
Section: Circuit Architecturementioning
confidence: 99%
“…The shunt RC feedback circuit used in [14] can increase bandwidth, flatten the gain and reduce the distortion. However, the peak gain will be degraded [30]. The neutralization capacitor technique can also achieve stability and increase the bandwidth of PA, and better gain can be maintained.…”
Section: Circuit Architecturementioning
confidence: 99%
“…An important criterion that designers should consider when using a transformer is the amount of power delivered from the source to the load, especially in applications such as WPT [3], [25], and impedance transformation in power amplifiers [1], [2], [4], [21], [22], [29]. We can assess the efficiency of the network with regard to the power from the transducer power gain G T , which is defined as the ratio of the power delivered to load P L to the power available from source P avs [16]:…”
Section: B Impedance Matching With Two Magnetically Coupled Coilsmentioning
confidence: 99%
“…In this study, an onchip transformer was designed in a 0.18 µm CMOS process by using an 8.625 µm thick back-end-of-line (BEOL) stack and a 300 µm thick silicon substrate. The complex dielectric stacks from the BEOL process were simplified into 14 equivalent dielectric layers, each of which was calculated on the basis of a series capacitance approximation verified in previous works [2], [4], [32], [33]. The conductivity of the substrate was set to 10 S/m.…”
Section: Verification Of the Proposed Analysis With An On-chip Tmentioning
confidence: 99%