An Ultra-Wideband 7-Bit 5 Gsps ADC Implemented in Submicron InP HBT Technology

Chan, Catherine S.; Oyama,; Monier,; Gutierrez, Bernardo

doi:10.1109/csics07.2007.41

Cited by 15 publications

(2 citation statements)

References 5 publications

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“…Applications such as software-defined radio, multi-standard systems, direct digital wireless receivers, wideband radar, as well as ultra-wideband (UWB) transceivers, require ADCs with signal bandwidths on the order of several gigahertz along with medium-to-high resolutions (8-10 bits). Besides, wideband, medium-to-high resolution ADCs are required in broadband communication data links and high-speed measurement and test instruments such as real-time high-speed oscilloscopes [2]- [5].…”

Section: Motivationmentioning

confidence: 99%

“…iii In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5 th -order, 1 GHz, Butterworth G m -C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm 2 . The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mV pp for the subsequent ADC stage.…”

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A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters

Mazlouman

Mirabbasi

2007

IEEE Trans. Circuits Syst. II

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Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as timeinterleaved structures are used. Unfortunately, such architectures require high-speed highprecision sample-and-hold (S/H) stages that are challenging to implement. In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth.

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Section: Motivationmentioning

confidence: 99%

mentioning

confidence: 99%

A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters

Mazlouman

Mirabbasi

2007

IEEE Trans. Circuits Syst. II

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A high-speed sample-and-hold circuit based on CMOS transmission lines

Wang

Gao

et al. 2010

Analog Integr Circ Sig Process

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We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 lm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of *50 ps width with *17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Gigasample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.

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An ultra low die area 8-b ADC and its generic calibration logic

Petrellis

Birbas²

2011

Analog Integr Circ Sig Process

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The 8-bit voltage mode subrange A/D converter described in this paper operates in a mid-input signal frequency range of up to 20 MHz and requires at least an order of magnitude lower die area (0.06 mm 2 ) than other A/D converters with a similar resolution. Moreover, it dissipates only 4.5 mW power and is supported by a calibration logic that is general enough to be used by several other measurement and instrumentation applications that require a real time adjustment of the amplitude and the level of their differential signals. This voltage mode subrange A/D converter architecture is actually an asynchronous two-step A/D converter that is based on a novel integer division operation. The current mode implementation of such an integer divider has already been employed by the authors in an innovative low area/power binary tree A/D conversion architecture. The voltage mode implementation of the integer divider allows the realization of the higher speed and lower power/area subrange A/D converter that is presented in this article.

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An Ultra-Wideband 7-Bit 5 Gsps ADC Implemented in Submicron InP HBT Technology

Cited by 15 publications

References 5 publications

A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters

A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters

A high-speed sample-and-hold circuit based on CMOS transmission lines

An ultra low die area 8-b ADC and its generic calibration logic

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