An ultra-low power voltage regulator for wireless sensor nodes

Gruber, Stefan; Reinisch, Hannes; Unterassinger, Hartwig; Wiessflecker, Martin; Hofer, Günter; Pribyl, Wolfgang; Holweg, Gerald

doi:10.1109/icm.2010.5696121

Cited by 3 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, the error signal drives the output pass transistor to regulate the output voltage. A simplified analysis of noise begins with tracing a subset of the loop represented by a common amplifier variation known as a voltage follower or power buffer [21][22][23][24][25]. This voltage follower circuit forces output voltage to follow .…”

Section: Ldo Topologymentioning

confidence: 99%

Design consideration in low dropout voltage regulator for batteryless power management unit

Kamel¹,

Wong²

2019

Bulletin EEI

View full text Add to dashboard Cite

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

show abstract