An Ultra-Low-Power Super Regeneration Oscillator-Based Transceiver With 177-$\mu$W Leakage-Compensated PLL and Automatic Quench Waveform Generator

Park, Hyung-Gu; Lee, Juri; Jang, Jeong-a; Jang, Jae-Hyeong; Lee, Dong‐Soo; Kim, Hong-Jin; Kim, Seong Joong; Lee, Sang‐Gug; Lee, Kang-Yoon

doi:10.1109/tmtt.2013.2274964

Cited by 8 publications

(3 citation statements)

References 11 publications

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“…16 and 17 respectively. Receivers are categorized into three architectures: Clocked-demodulators [13,[34][35][36][46][47][48][49][50][51][52][53][54], envelope-detectors [3,22,23,30,39,55], and super-regenerative [19,26,32,41,56,57]. Figure 17 shows that some clocked-demodulator-based receivers consume just as low power as envelope-detector-based and super-regenerative receivers by replacing a PLL with a high-Q resonator [34], or turning off the PLL during the receiver operation [13].…”

Section: Benchmarkingmentioning

confidence: 99%

Introduction to Ultra Low Power Transceiver Design

Lee

Mercier

2015

Integrated Circuits and Systems

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Design of radios with ultra-low-power consumption can enable many new and exciting applications ranging from wearable healthcare to Internet of Things devices and beyond. Achieving low power operation is usually an exercise in trading-off important performance metrics with power. This chapter presents an overview of state-of-the-art narrowband architectures and techniques that achieve ultra-low-power operation, and concludes with a section that benchmarks recent state-of-the-art designs in order to illustrate power-performance trade-offs.

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Section: Benchmarkingmentioning

confidence: 99%

Introduction to Ultra Low Power Transceiver Design

Lee

Mercier

2015

Integrated Circuits and Systems

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“…Looking at the previous work, this calibration mainly involves frequency synthesis of the super-regenerative oscillator (SRO), periodic current quenching waveform generation, and sampling timing of ADC [1][2][3]. Here, the frequency synthesis and current quenching waveform generation are the calibration fields associated with the multi-channel operation, receiver sensitivity, and selectivity performance.…”

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confidence: 99%

Robust super‐regenerative receiver with low susceptibility on clock jitter employing synchronous peak‐held envelope detector

Kim

2018

Electron. lett.

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A robust 400 MHz super-regenerative receiver with low susceptibility to clock jitter is proposed. The conventional un-clocked envelope detector (ED) is replaced with a synchronous peak-held ED, where its peak detection value is kept during oscillator quenching OFF time by switching off the charging path of ED, synchronously with quenching clock. In this way, the flattened peak level not only allows the use of low quality jitter in the clock but also removes a tedious timing calibration process in the conventional receiver. The proposed receiver with the novel synchronous peak-held ED and an on-chip oscillator achieves a sensitivity performance of −81 dBm@1 Mbps without the conventional ADC sampling timing calibration. The receiver in 180 nm CMOS occupies an active area of 0.51 mm 2 and dissipates 570 µW.

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“…Since WSN consists of a large number of self-powered sensor nodes, low-power consumption for the sensor nodes is very important to extend the battery lifetime. Many ultra-low power on-off keying (OOK) receivers are proposed with super-regenerative (SR) architecture [1,2]. To simplify the OOK receiver design, the direct demodulation architecture is proposed to achieve low-power and high-data rate merits [3][4][5].…”

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confidence: 99%

9.5 mW fully integrated K ‐band on–off keying receiver with −47.6 dBm sensitivity and 600 Mbit/s data rate in 90 nm CMOS

Chiou

Chien

2016

Electron. lett.

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A K-band on-off keying (OOK) receiver implemented in tsmc TM 90 nm CMOS process is proposed. The proposed OOK receiver consists of a two-stage wideband low-noise amplifier, a single-to-differential envelop detector with RC lowpass filter and a 62.6 dB three-stage variable gain amplifier and DC offset compensation circuit. The OOK receiver achieved a sensitivity of −47.6 dBm at 600 Mbit/s data rate under a pseudo-random binary sequence 2 9-1 pattern. The receiver consumes a low power of 9.5 mW, which minimum average power is only 15.86 nW at the input power of −47.6 dBm. The chip area including test pads is 1 × 0.81 mm 2 .

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An Ultra-Low-Power Super Regeneration Oscillator-Based Transceiver With 177-$\mu$W Leakage-Compensated PLL and Automatic Quench Waveform Generator

Cited by 8 publications

References 11 publications

Introduction to Ultra Low Power Transceiver Design

Introduction to Ultra Low Power Transceiver Design

Robust super‐regenerative receiver with low susceptibility on clock jitter employing synchronous peak‐held envelope detector

9.5 mW fully integrated K ‐band on–off keying receiver with −47.6 dBm sensitivity and 600 Mbit/s data rate in 90 nm CMOS

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