An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

Gassoumi, Ismail; Touil, Lamjed; Ouni, Bouraoui; Mtibaa, Abdellatif

doi:10.1155/2019/1675169

Cited by 17 publications

(9 citation statements)

References 30 publications

(58 reference statements)

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“…The BCH encoders can also be implemented using other higher forms such as (15, 11, 1), (15, 7, 2), and (31, 16, 3). Energy Dissipation of SCCC encoder [7] Proposed Fig. 13 Comparison of energy dissipation of the components of SCCC encoder…”

Section: Discussionmentioning

confidence: 99%

“…The architectures of the multiplexers from [5] are used to design D flip-flops. Designed D flip-flops are used to implement shift registers which are efficient than the ones in [6,7]. These shift registers are basic blocks of the serial-to-parallel converter (SPC) and parallel-to-serial converter (PSC) that are further used in the Outer Encoder and PRI stages of the SCCC encoder.…”

Section: Related Workmentioning

confidence: 99%

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Analysis of QCA-Based Serial Concatenated Convolution Coding Encoder for Error Correction

Dhanush¹,

Parashar²,

Premananda³

2021

Lecture Notes in Electrical Engineering

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Analysis of QCA-Based Serial Concatenated Convolution Coding Encoder for Error Correction

Dhanush¹,

Parashar²,

Premananda³

2021

Lecture Notes in Electrical Engineering

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“…The SCCC encoder divided into three fragments namely, OE, inter-leaver and inner encoder (IE). The designing of these fragments consists of SPC and PSC designed using the shift registers in [10].…”

Section: Related Workmentioning

confidence: 99%

Area and Energy Efficient QCA Based Compact Serial Concatenated Convolutional Code Encoder

Premananda¹,

Dhanush²,

Parashar³

2022

J. Phys.: Conf. Ser.

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Quantum-dot Cellular Automata (QCA) is a transistor-less technology known for its low power consumption and higher clock rate. Serial Concatenated Convolutional Coding (SCCC) encoder is a class of forward error correction. This paper picturizes the implementation of the outer encoder as a (7, 4, 1) Bose Chaudhary Hocquenghem encoder that serves the purpose of burst error correction, a pseudo-random inter-leaver used for permuting of systematic code words and finally the inner encoder which is used for the correction of random errors in QCA. Two different architectures of the SCCC encoder have been proposed and discussed in this study. In the proposed two architectures, the first based on external clock signals whereas the second based on internal clock generation. The sub-blocks outer encoder, pseudo-random inter-leaver and inner encoder of the SCCC encoder are optimized, implemented and simulated using QCADesigner and then integrated to design a compact SCCC encoder. The energy dissipation is computed using QCADesigner-E. The proposed SCCC encoder reduced the total area by 46% and energy dissipation by 50% when compared to the reference SCCC encoder. The proposed encoders are more efficient in terms of cell count, energy dissipation and area occupancy respectively.

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“…QCA-Pro 1.1-2, a power-analysis tool is used in this work to calculate the power-dissipation of proposed circuit [21]. This power performed at temperature 4 K and 1.0 Ek kink energy, which depends on the temperature of the design.…”

Section: Power Model Of "Qca"mentioning

confidence: 99%

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

Sarkar¹

2021

pae

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An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, can be optimized by “QCA” nano technology with electro-spin criterion and this technology also supports reversible logic in multilayer 3D platform with less complexity. This paper, primarily presents two novel “QCA” based 3-layered “Adder-Subtractor” designs using the collaboration of multilayer inverter gates, reversible modified 3-input Feynman-Gate and 3-input MG (Majority Gate) with very less cell-complexity, area-occupation, delay and energy-dissipation and high output-strength, temperature-tolerance and accuracy. A clear parametric investigation on presented designs are shown clearly in this paper through a comparative manner with some previous published related structures. Additionally, another parametric-experiment on a novel multibit reversible multilayer “QCA” based “Full-Adder-Subtractor” circuitry using the working phenomenon of “Ripple Carry Adder” (RCA) and multibit subtractor (“ripple borrow subtractor” or RBS) is presented in this proposed work in a proper way and this combination of RCA and multibit subtraction operation converts the proposed circuitry into a hybrid form, which is more effective compare to some other advanced adders in parametric-optimization field.

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An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

Cited by 17 publications

References 30 publications

Analysis of QCA-Based Serial Concatenated Convolution Coding Encoder for Error Correction

Analysis of QCA-Based Serial Concatenated Convolution Coding Encoder for Error Correction

Area and Energy Efficient QCA Based Compact Serial Concatenated Convolutional Code Encoder

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

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