An ultra low power encoder for 5 bit flash ADC

Lavania, Yatish; Varghese, George Tom; Mahapatra, Kamalakanta

doi:10.1109/icevent.2013.6496578

Cited by 6 publications

(7 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this case, the supply current from the translation were held constant. Then the change in power consumption can be estimated: at another bit by the coefficient [9]. Table 2 under the conditions of winning based on estimates of power consumption circuitry solutions developed encoder compared to known analogs is table.…”

Section: Materials and Methods Simulation Resultsmentioning

confidence: 99%

“…Power characteristics of the encoder performed using MOSFETs Cadence Virtuoso based on 180 nm CMOS technology from UMC to 1.8 V single supply [9]. Delay time-shift eight-evaluated by the response of the encoder output LSB Y8 direct binary code when the input code in the thermometric all 255 bits of logic zero to logic one on the front, and vice versa trailing edge, due to the encoder circuit solution.…”

Section: Materials and Methods Simulation Resultsmentioning

confidence: 99%

“…Clock frequency. Winning on the power consumption of circuit solutions presented encoder compared to known analogs [8][9][10] can evaluate on the basis of the simulation results. It is necessary to implement the conversion of power consumption being compared encoder (P ref ) the equivalent Encoder, executed in the same way, 8-bit word length, manufactured in 180 nm CMOS technology and has a clock speed of 1 GHz.…”

Section: Materials and Methods Simulation Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Design and Implementation of Double Base Integer Encoder of Term Metrical to Direct Binary

Smadi¹

2013

JSIP

View full text Add to dashboard Cite

The digital processing signal is one of the subdivisions of the analog digital converter interface; data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of low power operation power with 70 mVt 1.8 V A/D converter from the power dissipated during operation in the 5 GHz range. Average offset is used to minimize the effect of the bias of a comparator. This paper contains the 8-bit encoder of the metrical term code to direct binary code decreasing power consumption, which is shown by results and comparison with other designs using computer simulation. The results of the flash ADC time-interleaved are a more significant improvement in terms of power and areas than those previously reported.

show abstract

Section: Materials and Methods Simulation Resultsmentioning

confidence: 99%

Section: Materials and Methods Simulation Resultsmentioning

confidence: 99%

Section: Materials and Methods Simulation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Design and Implementation of Double Base Integer Encoder of Term Metrical to Direct Binary

Smadi¹

2013

JSIP

View full text Add to dashboard Cite

show abstract

“…In the domain of flash ADC (Analog-to-Digital Converter) design, circuits have been proposed to exploit such relationship and convert a thermometer code into a binary code using ASIC technology [9]. Because the basic circuit elements in FPGA and ASIC are different, these circuits cannot be transplanted directly into our TDC design.…”

Section: Encoding For Thermometer Codementioning

confidence: 99%

A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA

Song¹,

Wang²,

Kuang³

2018

J. Inst.

View full text Add to dashboard Cite

A: Field Programmable Gate Arrays (FPGAs) made with 28 nm and more advanced process technology have great potentials for implementation of high precision time-to-digital convertors (TDC), because the delay cells in the tapped delay line (TDL) used for time interpolation are getting smaller and smaller. However, the bubble problems in the TDL status are becoming more complicated, which make it difficult to achieve TDCs on these chips with a high time precision. In this paper, we are proposing a novel decomposition encoding scheme, which not only can solve the bubble problem easily, but also has a high encoding efficiency. The potential of these chips to realize TDC can be fully released with the scheme. In a Xilinx Kintex-7 FPGA chip, we implemented a TDC system with 256 TDC channels, which doubles the number of TDC channels that our previous technique could achieve. Performances of all these TDC channels are evaluated. The average RMS time precision among them is 10.23 ps in the time-interval measurement range of (0-10 ns), and their measurement throughput reaches 277 M measures per second. K: Front-end electronics for detector readout; Instrumentation and methods for time-offlight (TOF) spectroscopy; Timing detectors; Gamma camera, SPECT, PET PET/CT, coronary CT angiography (CTA)

show abstract

“…Block diagram of the Flash ADC is depicted in Fig. 1 (Lavania, Y et al, 2013). The three major components of Flash ADC are resistor ladder, comparator and an encoder.…”

Section: Introductionmentioning

confidence: 99%

Efficient Design Techniques of Flash ADC for High Speed and Ultra Low Power Applications

S.S.Kamate¹

2020

Biosci. Biotech. Res. Comm

View full text Add to dashboard Cite

Analog to Digital converters are the essential components of todays digital world. As these convert real time signal into its equivalent digital code, must be designed efficiently. This paper presents design of 3-bit high speed and power efficient Flash Analog to Digital Converter. Flash type Analog to Digital Converter is designed and implemented with different inverter based comparators and based ROM encoder. A high speed ROM encoder is designed to convert thermometer code to its equivalent binary code. The proposed research compares various inverter based comparators such as Threshold Inverter, Quantizer comparator, Single Inverter Comparator, Single Inverter Comparator with the reference voltage and LTE comparators, designed using cadence design tools with 180nm technological library. The simulation results show that Single Inverter Comparator consumes less power 5.647uW among TIQ and R-TIQ comparators. Single Inverter comparator with reference voltage consumes less power however with more delay. Here Flash ADCs are designed with various inverter based comparators and ROM encoder. The results show that TIQ comparator based ADCs consume power of 298.9uW, whereas ADC designed with Single Inverter Comparator consumes 459.8uW power.

show abstract

An ultra low power encoder for 5 bit flash ADC

Cited by 6 publications

References 3 publications

Design and Implementation of Double Base Integer Encoder of Term Metrical to Direct Binary

Design and Implementation of Double Base Integer Encoder of Term Metrical to Direct Binary

A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA

Efficient Design Techniques of Flash ADC for High Speed and Ultra Low Power Applications

Contact Info

Product

Resources

About