An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

Abstract

Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 W, 59.7 W and 71.1 W. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.

Methodology for Power-Performance Trade-Off Management in Real-Time Embedded Applications

“…To simplify the analysis, the utilization bound of U bound → 1 is assumed. Because the adopted value for utilization bound, case 2 is removed from possible workload execution scenarios defined in (13). Additionally, as the execution case 1 corresponds to the workload execution without deadline misses, and therefore without performance degradation, this scenario is also excluded from execution use cases presented in Figure 2.…”

“…Although the traditional approaches for designing low-power embedded systems vary, from simply relying on semiconductor manufacturers offering low power products, to more complex workload scheduling, there is no single universally accepted methodology applicable in all use cases. Ordinarily, it is a combination of component, circuit, system, application design, and associated trade-offs [8,[10][11][12][13][14]. In general, extensive optimization of embedded systems for low power consumption requires balancing between the application performance and system power usage.…”

“…Microprocessor and microcontroller manufacturers are offering different options for balancing the processing workload against consumed power. A common solution to bridge the gap between high performance and low power is to allow processors to run at different performance levels depending on the current workload [13,15,16]. In addition, standard operating systems (OSs) are offering services, dedicated for general purpose applications, to coordinate power management activities based on power policy settings.…”