An Ultra-Low Power Consumption High-Linearity Switching Scheme for SAR ADC

Chen, Yushi; Zhang, Yiqi; Tang, Hualian

doi:10.1142/s0218126620500863

Cited by 6 publications

(5 citation statements)

References 21 publications

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“…Tis technique leads to a reduction in the overall capacitance by one over eight. Similarly, the split of the dummy capacitor into two capacitors C-2C has been employed in [28,[49][50][51], as shown in Figure 15. Tis technique reduces the average energy by up to 99.6% and the area of the capacitor by up to 87.21% [51].…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…Te hybrid capacitor techniques [28,30,[49][50][51]] combine diferent techniques. Such as the binary-weighted and unary capacitor, that has been achieved in [30].…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…Utilizing the C-2C dummy capacitor technique, a twostage subarray capacitor technique and the charge-sharing voltage switching scheme [28] has led to boosting the linearity and capacitors matching. As well, work [49] has employed the C-2C dummy capacitor technique, and the charge-sharing scheme to enhance the linearity. Another work [50,51] has utilized the C-2C dummy capacitor technique with foating capacitor scheme.…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…While the two-step reset method employs an intermediate stage between the fnal and the initial states to achieve zero reset energy consumption, this technique has been used in [28,41,42,49,50,56].…”

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…Te hybrid capacitor techniques [28,30,[49][50][51]] combine diferent techniques. Such as the binary-weighted and unary capacitor, that has been achieved in [30].…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

See 2 more Smart Citations

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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show abstract

“…Tang [13] reviewed design techniques for a low power SAR ADC. In the work, noise analysis of comparator in terms of kickback noise analysis and jitter analysis in DAC module of SAR Further In order to enhance the speed and reduction of the power consumption of the SAR ADC, an asynchronous method is implemented [14][15][16]. Additionally, efforts have been made to reduce the complexity and area of the control logic for SAR.…”

Section: Introductionmentioning

confidence: 99%

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

Tyagi,

Mittal,

Kumar

2023

Phys. Scr.

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The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

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