An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive $V_{\rm DD}$ System for Wireless Sensor Networks

Lin, Tong; Chong, Kwen-Siong; Chang, Joseph S.; Gwee, Bah-Hwee

doi:10.1109/jssc.2012.2223971

Cited by 38 publications

(31 citation statements)

References 31 publications

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“…In this sense, our characterization herein provides good insight for the design and implementation of future complex and reliable RHBD digital circuits and systems [7], [8].…”

Section: Introductionmentioning

confidence: 82%

Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process

Chang

Chong

Shu

et al. 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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We propose a radiation-hardened library cell template based on a 65nm CMOS process for the development of a radiation-hardened-by-design (RHBD) cell library for space and satellite (S&S) applications. The proposed library cell template adheres to the fixed-height variable-width standard cell approach, and is designed to inherently embody a number of RHBD techniques at the device-and layout-level to mitigate the radiation effects. We further design a test circuitry embodying several library cells based on the RHBD template for total ionizing dose (TID) irradiation testing. With the test circuitry, we show that our RHBD library cells experience insignificant delay effects at TID dosage up to 500Krad, V DD = 0.9V−1.4V. The irradiating tests provide concrete experimental data that verify the robustness of our proposed RHBD cell template and the ensuing design methodologies (including library development) for S&S electronics.

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“…In this sense, our characterization herein provides good insight for the design and implementation of future complex and reliable RHBD digital circuits and systems [7], [8].…”

Section: Introductionmentioning

confidence: 82%

Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process

Chang

Chong

Shu

et al. 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

Self Cite

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“…Instead, an asynchronous-logic (async) methodology could be in part adopted to circumvent such data synchronization issue. The basic premise is that async circuits are essentially self-timed circuits by using async handshake protocols [3], [4] to synchronize digital operations.…”

Section: Introductionmentioning

confidence: 99%

“…Particularly, in near-to sub-threshold operations, the on-current (I on ) of the transistor, consequently the associated circuit delay, are exponentially dependent on PVT variations [4]. Hence, not unexpectedly, the delay-variation (and the worst-case delay) of the A2S-IC increases significantly, hence unnecessarily slowing down the entire system.…”

Section: Introductionmentioning

confidence: 99%

Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips

Chong

Gwee

et al. 2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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We propose an Asynchronous-to-Synchronous Interface Controller (A2S-IC) with low delay-variation towards Process, Voltage and Temperature (PVT) variations for subthreshold/near-threshold operation in low power applications. This A2S-IC is targeted for a full-range Dynamic Voltage Scaling (DVS) Global-Asynchronous-Local-Synchronous (GALS) Network-on-Chip (NoC). There are three key attributes in this proposed A2S-IC. First, it is realized using static-logic (over dynamic-logic), hence is more appropriate for DVS (and subthreshold operation). Second, it is implemented using gate-level standard-cell to simplify the implementation efforts. Third, it is designed to share some internal nodes, hence reducing the redundant switching for data validity checking. The proposed A2S-IC is compared against its reported dynamic-logic counterpart; both are implemented in the same 65nm CMOS process. Based on the simulations conducted at 27°C, our proposed A2S-IC is more throughput-efficient at near-and subthreshold operations, featuring ~19% and ~66% faster throughput at V DD =0.5V and V DD =0.3V respectively. When the temperature variation (0°C to 100°C) is considered at the subthreshold operation, the proposed A2S-IC demonstrates 140% faster throughput than the reported design, the former only features up to 1.6× delay-variation but the latter exhibits up to 4× delay-variation. The proposed A2S-IC is able to operate at the voltage as low as 0.15V (as opposed to 0.3V for the reported design).

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“…The rapid advancement of the electronic technology has resulted in numerous applications, including space projects [1,2], defense projects [3][4][5], mobile/portable devices [6,7], wireless-sensor-networks [8,9], Internet-of-Things [10,11], multi-core processors [12,13], etc. In these applications, digital communication and processing capabilities are collectively integrated in Systems-on-Chip (SoC) or Systems-in-Package using the advanced nano-scaled fabrication processes.…”

Section: Introduction 11 Motivationmentioning

confidence: 99%

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Zhou¹

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In the past decades of electronic circuit designs, the synchronous-logic (sync) is the main de-facto design approach for digital systems. This is largely due to its synchronization to a global clock signal (or its variants thereof) which simplifies the data transfer. Nevertheless, designing digital circuits and systems based on sync approach is becoming more challenging due to the increase in process, voltage and temperature (PVT) variations in the deep submicron fabrication process. An alternative design approach which is based on the asynchronous-logic (async), is

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An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive $V_{\rm DD}$ System for Wireless Sensor Networks

Cited by 38 publications

References 31 publications

Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process

Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process

Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

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