An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications

Abstract

Abstract-In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with conventional approaches. Besides, the proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Measurement results show that power consumption of the proposed DCO can be improved to 140 W (@200 MHz) with 1.47-ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.Index Terms-All-digital phase-locked loop (ADPLL), cell-based design, digitally controlled oscillator (DCO), hysteresis delay cell (HDC), portable, segmental delay line (SDL).

Digitally Assisted Analog and RF Circuits

“…A digitally-controlled varactor can be realized by a NAND gate [31], [32], [34] as shown in Fig. 19, and a digitally-controlled oscillator (DCO) can also be realized by MUXs and the digitally-controlled varactor [35]. In addition, a phase-interpolator-based oscillator can be employed and synthesized to mitigate the layout uncertainty issue [31], [32], [36].…”

A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

“…The Fine DDCC is added to further improve the resolution of the proposed dutycycle correction circuit. In the Fine DDCC, the digitally controlled varactors (DCVs) [8] are applied to improve the resolution of the fine-tuning delay cell to about 3 ps.…”

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

“…Therefore, (7) reduces to (8) Consequently, the expected absolute-squared value of the received signals is determined by the power of both the filter response and AWGN. Based on the SIR definition, (8) is rewritten as (9) where is the interference power of the filter tail.…”

“…Unlike multirate sampling methods [1]- [3], this DSTC requires aided circuits in a clock source design to generate a phase-tunable clock waveform that corresponds to the best sampling instance as calculated by the DSTC. A digitally-controlled oscillator (DCO) design concept [9] is applied to the phase-tunable clock generator (PTCG) design to enable this symbol-rate DSTC [10] for low-power wireless applications.…”