An ultra high step‐up DC‐DC converter based on VMC, POSLLC, and boost converter

Abstract

In this article, an ultra‐high step‐up DC‐DC converter has been proposed. The topology of the converter is a combination of a cascaded boost converter, positive output super lift Luo converter (POS LLC), and a voltage multiplier cell (VMC). The lower values of the duty cycle provide a more than 10 times voltage gain. Consequently, the high voltage gain has been provided beside the lower value of the voltage/current stress of the semiconductor and an acceptable value of the efficiency. With a detailed look, it can be understood the voltage gain and efficiency of the converter have become 12 times and 90.5% based on the experimental results while the percentage of the duty cycle has become 50%. Moreover, by the mentioned percentage of the duty cycle, the normalized value of the voltage/current stress of the semiconductors has become lower than 50% by exception of only 3 semiconductor‐based components which have voltage/current stresses more than 50% and lower than the unity. In addition to all the mentioned advantages, the input current has remained continuous which solves the challenges of the input filter's capacitor. Moreover, the voltage/current stresses have been kept low‐valued. The ideal mode of the topology has been discussed for both continuous/discontinuous current modes. The non‐ideal mode of the topology and its related comparisons have been done. A comparison of the voltage/current stresses of the semiconductor‐based components has been done. Moreover, the comparison of the losses and efficiency have been done for the proposed converter and recently suggested topologies. In addition, the efficiency has been discussed for the different values of its effective factors and the resulted behavior has been expressed. Finally, the simulation and experimental outcomes have been extracted for a 120 W output power and compared with the theoretical relations' results.

A Quadratic Buck-Boost Converter With Continuous Input and Output Currents

“…The diode conduction loss in the proposed converter is lower than [1]- [4], [7]- [9], [12]- [14], but higher than [5], [6], [11]. The proposed efficiency is higher than [2]- [4], [7], [8], [12]- [14], but similar to [1], [5], [6], [9]- [11].…”

“…Based on the mentioned parameters, the governing equation of the voltage gain in DCM is expressed as (8).…”

“…Table 5 compares various losses of the proposed converter and [1]- [14]. The proposed topology has higher extracted inductor loss than [1]- [8] and [8]- [14], but lower extracted switch loss than [2]- [4], [7], [8], [12]- [14]. The diode conduction loss in the proposed converter is lower than [1]- [4], [7]- [9], [12]- [14], but higher than [5], [6], [11].…”

“…The appeared inrush currents have less effect than previous ones, but the input current ripple is increased. The proposed topology in [8] is a combination of an improved boost converter with a VMC and a super lift Luo converter that improves the voltage gain but increases conduction loss and current stress due to inrush currents. A proposed topology [9] eliminates the common ground of the input source and load to increase the voltage gain but increases the input current ripple and the number of diodes, which decreases reliability.…”

A novel high‐efficient step‐up converter with continuous input current, common ground, and minimum stress on semiconductors

“…In solar cell applications, the input voltage varies between 15 and 60 V, which is insufficient for supplying the grid-connected inverters' DC bus. Furthermore, step-up converters increase cars' battery voltage to the required voltage level for high-intensity discharge (HID) lamps used in the cars' lighting system [12,13].…”