An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture

Park, Jeong-In; Yeon, Jewong; Yang, Shaopeng; Lee, Hanho

doi:10.1109/isocc.2012.6406893

Search citation statements

Order By: Relevance

Paper Sections

Select...

B Galois Field Multiplier (2 8 )1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2012

2018

Publication Types

Select...

Other5

Relationship

Self Cite0

Independent5

Authors

Journals

Cited by 12 publications

(1 citation statement)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Multiplexer selection (3) and (4) becomes 1 after all the clock cycle performed by one syndrome calculation, to shift syndromes S i to the latch (2) and to compute new received codeword. Three-parallel syndrome computation has to be done by equation (8).…”

Section: B Galois Field Multiplier (2 8 )mentioning

confidence: 99%

Three-parallel syndrome computation block for RS decoder

Ghodeswar

Surkar

Sarate

2014

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)

View full text Add to dashboard Cite

This paper presents a design of syndrome computation block for Reed-Solomon decoder for RS (255, 239) code. For calculating the syndromes, three-parallel processing has been used. Parallelizing allow inputs to be received at very high rates and outputs to be delivered at correspondingly high rates with minimum delay. RS (255, 239) code consists of 255 symbols which are multiple of 3. So three symbols are inputted parallely in syndrome computation block. This process can be adapted in the FEC devices.

show abstract

Section: B Galois Field Multiplier (2 8 )mentioning

confidence: 99%