An Ultra-Fast Parallel Prefix Adder

Pandey, Kumar Sambhav; B, Dinesh Kumar; Goel, Nishith; Shrimali, Hitesh

doi:10.1109/arith.2019.00034

Cited by 15 publications

(6 citation statements)

References 14 publications

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“…Its symmetry and regular construction structure greatly decreases production costs and allows it to be employed in pipelined topologies. With a chip size of O (n log n), the addition of n-bit numbers can be done in time O (log n), making it a good choice when there are area limitations while maximizing performance [11].…”

Section: Brent-kung Addermentioning

confidence: 99%

Design of novel high speed parallel prefix adder

Athur

Narayanan²,

Gopalakrishnan³

et al. 2023

IJEECS

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Adders are crucial logical building blocks found almost in all the modern electronic system designs. In the adder architecture design, the fundamental issue is the propagation latency in the carry chain. As the length of the input operands increases, the length of the carry chain along with it. Parallel prefix adders, which address the problem of carry propagation in adders, are the most efficient adder topologies for hardware implementation. However, delay reduction still could be achieved for very high speed applications. Hence, in this paper design of 16bit novel parallel prefix adder is proposed and compared against the existing parallel prefix adder architectures. The design and simulation are carried out using xilinx vivado for field- programmable gate array (FPGA) simulation and Cadence® for ASIC. The results of ASIC implementation demonstrate 17.8% delay reduction while compared to sparse kogge-stone adder.

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Section: Brent-kung Addermentioning

confidence: 99%

Design of novel high speed parallel prefix adder

Athur

Narayanan²,

Gopalakrishnan³

et al. 2023

IJEECS

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show abstract

“…Adders come in different varieties, and each has a distinct function and significance [1]. The choice of adder type is contingent upon the intended application [2]. In order to achieve high accuracy and minimal space consumption, adders must be able to compute more quickly.…”

Section: Introductionmentioning

confidence: 99%

“…The carry chain is the main disadvantage of binary addition. [2] [3]. The carry chain's length grows in tandem with the width of the input operands.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Parallel Prefix Adders

Viraktimath,

et al. 2023

IJRASET

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Parallel prefix adders are essential components of contemporary digital arithmetic circuits and are found in many different devices, including digital signal processors and microprocessors. In order to improve the effectiveness and performance of parallel prefix adders, this research investigates their design and optimization. This paper analyses in detail the state of the parallel prefix adder architectures and provide new designs that minimize power consumption and critical path delays. The speed and area efficiency benefits of the parallel prefix designs with thorough simulations and comparisons is reviewed. This research have ramifications for high-performance computing systems and point to interesting avenues to further the state of the art in parallel prefix adder design.

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“…Though, bit-wise logical operations can be trivially performed in parallel at any sub-atomic data boundary, yet, the case of arithmetic or shift operations is not as straightforward due to the issue of carry/borrow propagation. This problem of carry/borrow propagation has been studied at length and various designs have been proposed [5]- [11]. The focus of all of these efforts has been on reducing the latency and/or increasing the throughput, albeit at the cost of increased area and power.…”

Section: Introductionmentioning

confidence: 99%

“…1. The semantics of blocks gpt, red, car and sum have been borrowed from [5], while the dark small rectangles are pipeline registers. Block gpt computes three signals Generate(g i ), Propagate(p i ) and Transmit(t i ) locally at individual bit positions i.…”

Section: Introductionmentioning

confidence: 99%

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

Pandey

Shrimali

2022

IEEE Access

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Parallelism is the key to enhancing the throughput of computing structures. However, it is well established that the presence of data-flow dependencies adversely impacts the exploitation of such parallelism. This paper presents a case for a new computing paradigm namely subscalar digital arithmetic which is aimed at mitigating this issue. It proposes to break up atomic data and atomic operations thereon into sub-atomic data fragments and sub-atomic partial operations. Such a break-up exposes hitherto unexploited levels of parallelism by way of allowing overlap of operations even if data-dependent. Surprisingly this enhanced exploitation of latent parallelism comes with a favorable impact on the area-power characteristics of corresponding computing structures which is contrary to common sense. The paper also proposes a novel micro cell library with logic primitives at corresponding subscalar levels. The synthesized circuits for several sequential benchmarks show an order of magnitude improvement in their area-throughput figure-of-merit (FOM).INDEX TERMS Bit-level parallelism, digital arithmetic, pipelining.

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An Ultra-Fast Parallel Prefix Adder

Cited by 15 publications

References 14 publications

Design of novel high speed parallel prefix adder

Design of novel high speed parallel prefix adder

Analysis of Parallel Prefix Adders

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

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