An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing

Toal, C.; Burns, D. C.; McLaughlin, Kieran; Sezer, Sakir; O'Kane, S.

doi:10.1109/ahs.2007.30

Cited by 9 publications

(4 citation statements)

References 10 publications

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“…This ensures its stability and future adoption. It is also already adopted in highspeed networking solutions [27], [28]. Moreover, RLDRAM is supported by several industry players such as Intel [37], Xilinx [38], Lattice [39], and Northwest Logic [40].…”

Section: Other Considerations: a Discussionmentioning

confidence: 99%

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On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?

Hassan

2018

2018 IEEE Real-Time Systems Symposium (RTSS)

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Predictable execution time upon accessing shared memories in multi-core real-time systems is a stringent requirement. A plethora of existing works focus on the analysis of Double Data Rate Dynamic Random Access Memories (DDR DRAMs), or redesigning its memory to provide predictable memory behavior. In this paper, we show that DDR DRAMs by construction suffer inherent limitations associated with achieving such predictability. These limitations lead to 1) highly variable access latencies that fluctuate based on various factors such as access patterns and memory state from previous accesses, and 2) overly pessimistic latency bounds. As a result, DDR DRAMs can be ill-suited for some real-time systems that mandate a strict predictable performance with tight timing constraints. Targeting these systems, we promote an alternative off-chip memory solution that is based on the emerging Reduced Latency DRAM (RLDRAM) protocol, and propose a predictable memory controller (RLDC) managing accesses to this memory. Comparing with the state-of-the-art predictable DDR controllers, the proposed solution provides up to 11× less timing variability and 6.4× reduction in the worst case memory latency.

show abstract

Section: Other Considerations: a Discussionmentioning

confidence: 99%

“…RLDRAM. RLDRAM memory is originally targeted at high-speed routers [27] and network processing [28]. Researchers also envisioned the usage of RLDRAM as a lowlatency memory module in a heterogeneous memory system to increase overall memory performance [29], [30].…”

Section: Related Workmentioning

confidence: 99%

On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?

Hassan

2018

2018 IEEE Real-Time Systems Symposium (RTSS)

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“…Reduced Latency DRAM (RLDRAM3 [30]) was designed as a deter− ministic latency DRAM module for use in high−speed applications such as network controllers [40]. While the pin−bandwidth of RL− DRAM3 is comparable to DDR3, its core latencies are extremely small, due to the use of many small arrays.…”

Section: Rldrammentioning

confidence: 99%

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access

Chatterjee

Shevgoor

Balasubramonian

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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The DRAM main memory system in modern servers is largely homogeneous. In recent years, DRAM manufacturers have produced chips with vastly differing latency and energy characteristics. This provides the opportunity to build a heterogeneous main memory system where different parts of the address space can yield different latencies and energy per access. The limited prior work in this area has explored smart placement of pages with high activities. In this paper, we propose a novel alternative to exploit DRAM heterogeneity. We observe that the critical word in a cache line can be easily recognized beforehand and placed in a low-latency region of the main memory. Other non-critical words of the cache line can be placed in a low-energy region. We design an architecture that has low complexity and that can accelerate the transfer of the critical word by tens of cycles. For our benchmark suite, we show an average performance improvement of 12.9% and an accompanying memory energy reduction of 15%.

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“…As a result, long DRAM latency remains as a significant system performance bottleneck for many modern applications [243,252], such as in-memory databases [11,37,64,221,361], data analytics (e.g., Spark) [22,23,64,366], graph traversals [7,351,365], pointer chasing workloads [116], CHAPTER 1. INTRODUCTION Google's datacenter workloads [154], and buffers for network packets in routers or network processors [16,110,174,344,356,371]. For example, a recent study by Google reported that memory latency is more important than memory bandwidth for the applications running in Google's datacenters [154].…”

Section: Introductionmentioning

confidence: 99%

Understanding and Improving the Latency of DRAM-Based Memory Systems

Chang

2017

Preprint

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An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing

Cited by 9 publications

References 10 publications

On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?

On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access

Understanding and Improving the Latency of DRAM-Based Memory Systems

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