An RDS, LEED, and STM Study of MOCVD-Prepared Si(100) surfaces

Selective area metalorganic vapor-phase epitaxy of gallium arsenide on silicon

“…1(b). This LEED pattern is analogous to that produced previously by MOVPE at temperatures from 850 to 900 1C, and by MBE at 650-850 1C [23][24][25].…”

“…1(b). The oxygen may have been removed from the surface as water by reaction with the hydrogen supplied from the TBA, or it could have desorbed as AsO, which has been observed on GaAs at 582 1C [24,26].…”

Improved structure and performance of the GaAsSb/InP interface in a resonant tunneling diode

“…The performance of these devices crucially depends on interface roughness, abruptness, and layer composition. A demanding issue of interface science, device development, and epitaxy is the understanding and the continuous improvement of III-V hetero-interfaces [1], as well as the interfaces between III-V-material and silicon [2] or III-V-material and germanium [3]. Interface issues are, for example, the effects of interfacial atomic segregation and intermixing and the role of the surface termination and reconstruction on the electronic properties of interfaces.…”

Optimizing diffusion, morphology and minority carrier lifetime in Silicon for GaAsP/Si dual-junction solar cells

“…Although the exposure of substrates (before growth) to a short PH 3 flush has been proven to be beneficial for obtaining a high quality GaP morphology [9][10][11]; we have demonstrated [12] that the effect of long PH 3 exposures at temperatures ranging from 800-875 °C (required for obtaining a deep enough emitter) will lead to an important degradation of the surface due to Si hydridation and subsequent dimmer displacement [13,14]. Therefore, in our quest for obtaining an optimized bottom subcell for a hybrid III-V-on-Si DJSC, we have assessed whether or not it is possible to form the emitter by P diffusion, while maintaining a high quality surface morphology on the silicon wafer.…”