An RBF-PSO technique for the rapid optimization of (CMOS) analog circuits

Garbaya, Amel; Kotti, Mouna; Drira, Nawel; Fakhfakh, Mourad; Tlelo‐Cuautle, Esteban; Siarry, Patrick

doi:10.1109/mocast.2018.8376657

Cited by 16 publications

(10 citation statements)

References 13 publications

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“…For the quick selection of optimum dimensions of CMOS Analog Circuits utilization of the substitution modeling strategies along with a grouping of meta-heuristics was projected in the research work carried out by Garbaya et al, (2018) [5]. Utilization of meta-modeling techniques within an optimization loop and demonstrating the benefits as their primary motivation.…”

Section: Work Proposed Bymentioning

confidence: 99%

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Maddileti¹,

Govindarajulu²,

Sivappagari³

2020

IJACSA

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Low Power Dissipation is an emerging challenge in the current electronics industry. Area shrinking has found the most prominent place and is the foundation of every constricted size in the utilization of CMOS circuits in Integrated Circuit Manufacturing. Functionality in terms of rapidity, dissipation of power, etc. are strongly influenced by the dimensions of transistors in many CMOS Integrated Circuits. The significant formulation parameters in CMOS circuit design to perform optimization of the above-mentioned parameters, and various techniques were projected earlier to a maximum extent possible. Latency, Power, and Dimension are significant parameters in the design of CMOS based IC design. Most analog circuit reduction in terms of size as parameter typically describes solitary or many objectives-controlled optimization issues. The eminent challenges with regards to size and power dissipation can be described as problems that are typically encountered under certain conditions. In this study, the design of a two-stage CMOS Differential Amplifier applying the nature-inspired Grey Wolf Algorithm for optimizing the area and power is utilized. To enhance the formulation terms concerning important considerations such as the amount incurred, strength, and functionality; a computerized formulation approach is used. This formulated design proposal will meet specifications such as positive and negative Slew Rate, Unity Gain Bandwidth and Phase Margin, etc. Chaos theory can be induced into the Grey Wolf Optimization Algorithm (CGWO) with the help of speeding global convergence metric i.e. Speed. The results obtained from CGWO are then analyzed with the functionality of other prevailing optimization techniques employed in the analog circuit sizing. Depending on the investigations, CGWO functions reduce the dimensions of the circuit and analyze the prevailing techniques by achieving a healthier rate of convergence and power dissipation with low value.

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Section: Work Proposed Bymentioning

confidence: 99%

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Maddileti¹,

Govindarajulu²,

Sivappagari³

2020

IJACSA

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“…An effective way to improve optimization efficiency is by introducing machine learning techniques into optimization [8], [10], [11], [12], [13], [14], [15]. Surrogate models, which are often constructed by machine learning techniques, are ideally computationally cheap approximation models of simulations.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

Budak

Gandara

Shi

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Machine learning-assisted global optimization methods for speeding up analog integrated circuit sizing is attracting much attention. However, often a few typical analog IC design specifications are considered in most relevant research. When considering the complete set of specifications, two main challenges are yet to be addressed: (1) The prediction error for some performances may be large and the prediction error is accumulated by many performances. This may mislead the optimization and fail the sizing, especially when the specifications are stringent. (2) The machine learning cost could be high considering the number of specifications, considerably canceling out the time saved. A new method, called Efficient Surrogate Model-assisted Sizing Method for High-performance Analog Building Blocks (ESSAB), is proposed in this paper to address the above challenges.The key innovations include a new candidate design ranking method and a new artificial neural network model construction method for analog circuit performances. Experiments using two amplifiers and a comparator with a complete set of stringent design specifications show the advantages of ESSAB.

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“…Multiple studies have reported the use of PSO for the optimization of analog circuit sizing. A few studies have also reported the use of a combination of PSO with other optimization techniques for the analog circuit area optimization [6], [7]. A modified version of PSO called hierarchical particle swarm optimization (HPSO) has been used for the optimization of component sizing of various analog circuits [8] .…”

Section: Introductionmentioning

confidence: 99%

Hybrid Particle Swarm Optimization Algorithm for Area Minimization in 65 nm Technology

Rashid

Nambath

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Analog design can be considered as a multidimensional optimization problem since it involves trade-offs between several circuit parameters. Various optimization techniques have been proposed to reduce the cycle time of analog design. We propose a hybrid particle swarm optimization algorithm with linearly decreasing inertia weight for the optimization of analog circuit design. The proposed method is validated in a differential amplifier circuit with a current mirror load. Promising simulation results demonstrate that the proposed method can significantly reduce the design time required for analog circuits.

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An RBF-PSO technique for the rapid optimization of (CMOS) analog circuits

Cited by 16 publications

References 13 publications

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

Hybrid Particle Swarm Optimization Algorithm for Area Minimization in 65 nm Technology

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