An overview of the Texas reconfigurable array computer

Sejnowski, Matthew C.; Upchurch, Edwin T.; Kapur, Rajan N.; Charlu, Daniel P. S.; Lipovski, G. Jack

doi:10.1145/1500518.1500623

Cited by 50 publications

(8 citation statements)

References 11 publications

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“…A processor Pi in cluster Cj can send data to a processor P j in cluster C j as shown in the Figure. P j sends the data to the DSPj , which sends the data to DSP j in a burst mode. DSP j then sends 48 the data to the processor Pj. We are evaluating both alternatives for intercluster commun--ication.…”

Section: Global Busmentioning

confidence: 99%

“…Hence, partitionability and dynamic resource allocations are keys to high performance. Much effort has been devoted towards investigating the partitionability of interconnection networks [47,48]. Approaches such as in [37,48] task, its associated data and the number of processors allocated for the task, the data is partitioned in such a way that each processor gets an equal or a comparable amount of computation [44].…”

Section: Partitioning and Resource Allocationmentioning

confidence: 99%

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Parallel Architectures and Parallel Algorithms for Integrated Vision Systems

Patel

Choudhary

1990

The Kluwer International Series in Engineering and Computer Science

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Computer vision has been regarded as one of the most complex and computationally intensive -problems. An integrated vision system (lVS) is a system that uses vision algorithms from all levels of processing to perform for a high level application (e.g, object recognition). An IVS normally A multiprocessor architecture for IVSs (called NETRA) is presented. NETRA is highly flexible without the use of complex interconnection schemes. NETRA is recursively defined hierarchical architecture whose leaf nodes consist of clusters processors connected with a programmable crossbar with a selective broadcast capability. Hence, it is easily scalable from small to large systems. Homogeneity of NETRA permits fault tolerance and graceful degradation under faults. Several refinements in the architecture over the original design are also proposed.Performance of several vision algorithms when they are mapped on one cluster is presented. It is shown that SIMD, MIMD and systolic algorithms can be easily mapped onto processor clusters, and almost linear speedups are possible. For some algorithms, analytical performance results are compared with those obtained using an implementation. It is observed that the analysis is very accurate.An extensive analysis of inter-cluster communication strategies in NETRA is presented. A methodology to evaluate performance of algorithms on NETRA is described. Performance analysis of parallel algorithms when mapped across clusters is presented. The parameters are derived from the characteristics of the parallel algorithms, which are then, used to evaluate the alternative communication strategies in NETRA. The effects of communication interference on the performance of algorithms are studied. It is observed that if communication speeds are matched with the computation speeds, almost linear speedups are possible when algorithms are mapped across clusters.Finally, several techniques to perform data decomposition, and static and dynamic load balancing for IVS afgorithms are described. These techniques can be used to perform load balancing for intermediate and high level, data dependent vision algorithms. These techniques are novel because they use knowledge about the data when it is produced and use knowledge about the computation in the next task to perform load balancing in an integrated environment. They are shown to perform well, using them on an implementation of a motion estimation system on a hypercube mUltiprocessor. attempting to define and solve pans of the problems for many years. However, to say that computer vision is in its infancy today is a correct judgment of the state of the an in artificial vision. Furthermore, nobody knows the answer to the question of whether it is possible to make artificial vision as powerful and general as human vision. One of the many reasons for not knowing the answer is that little is understood about human vision itself. LIST OF TABLESThere are several approaches to tackling the computational problems in computer vision. One of the approaches, which is also th...

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Section: Global Busmentioning

confidence: 99%

Section: Partitioning and Resource Allocationmentioning

confidence: 99%

Parallel Architectures and Parallel Algorithms for Integrated Vision Systems

Patel

Choudhary

1990

The Kluwer International Series in Engineering and Computer Science

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“…In this case, each virtual machine can be an SIMD machine or an MIND machine. Examples of proposed partitionable SIMD/MIMD systems are PASM and TRAC Sejnowski et al 1980]. …”

Section: Parallel Machine Organizationsmentioning

confidence: 99%

An introduction to the multistage cube family of interconnection networks

1987

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The interconneetion network in large-scale parallel/distributed supercomputer systems is a crucial component. Three networks are overviewed here. Multistage cube networks represent an important family of networks, which includes the omega, n-cube, multistage shuffle-exchange, delta, baseline, SW-banyan, and Generalized Cube. This family has been used or proposed for use in such systems as SIARAN, PASM, Ultracomputer, the BBN Butterfly. the IBM RP3, and data-flow machines. The multistage cube topology, distributed routing control, and ability to be partitioned into independent subnetworks are examined. The Extra Stage Cube (ESC), a single-faullt-tolerant multistage cube network, is described. The structure, control, and partitionability of the ESC, and how it functions when multiple faults occur, are p~esented. The Dynamic Redundancy (DR) network, a faulttolerant multistage cube network that supports the incorporation of spare processors for fault tolerance, is discussed. Its structure, control, and partitionability into single-fault-tolerant subnetworks are explained.

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“…This is called the processor-to-memory approach. This type of approach is used in'~'he B~[ 9 , 1 0 ] SIMD machine, the C.mmp [27] MIMD machine, and the TRAC [17] SIMD/MIMD machine. A third possibility is the PE-to-memory approach that is used in PUMPS [4].…”

Section: Definitionsmentioning

confidence: 99%

Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network

McMillen

Siegel

1982

SIGARCH Comput. Archit. News

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The Inverse Augmented Data Manipulator (IADM) is a multistage interconnection network based on the Augmented Data Manipulator (ADM) and Feng's data manipulator.It is designed to be used in largescale parallel/distributed processing systems for communication among processors, memories, and other system devices.Two aspects of IADM network design are discussed:performance and fault tolerance. A single stage look-ahead scheme for predicting blockage is presented to enhance performance.Next, one method of adding some links to the network to enable it to tolerate one link failure is described.Finally, a different method of adding links is shown that both improves performance and allows the network to tolerate two switching element or two link failures.Included is a new routing tag scheme that accommodates the new links.

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An overview of the Texas reconfigurable array computer

Cited by 50 publications

References 11 publications

Parallel Architectures and Parallel Algorithms for Integrated Vision Systems

Parallel Architectures and Parallel Algorithms for Integrated Vision Systems

An introduction to the multistage cube family of interconnection networks

Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network

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